Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2001-08-28
2002-10-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S315000
Reexamination Certificate
active
06461927
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a collector top heterojunction bipolar transistor, and particularly to a power amplifier high in power conversion efficiency.
With recent rapid increase in demand for mobile communication equipment, research and development of power amplifiers used for communication equipment have been made extensively. For example, JP-A-10-135750 discloses power amplifiers in which heterojunction bipolar transistors (HBTs) are used as semiconductor devices.
FIG. 23
shows a circuit diagram of a two-stage amplifier using a monolithic·microwave integrated circuit as an example of the power amplifiers. In
FIG. 23
, an input matching circuit as a circuit which determines the input impedance is connected for input and an output matching circuit as a circuit which determines the output impedance is connected for output. (These are not shown in the circuit diagram
23
because they are formed by an outer passive device outside the integrated circuit.) In order to improve the power conversion efficiency of the power amplifier as shown in
FIG. 23
, it is essential (1) to improve the power conversion efficiency of driver-stage HBT and output-stage HBT and (2) to reduce power consumption in bias circuit.
As for (1), it is effective to reduce the knee voltage of HBT (a minimum collector-emitter voltage at an operating maximum collector current). The knee voltage of HBT is determined depending on offset voltage (collector to emitter voltage when collector current becomes zero) and emitter resistance and collector resistance. It is known that the off-set voltage of HBT is lower in collector top HBT having a collector formed on the surface side than in emitter top HBT having an emitter formed on the surface side, and a collector top HBT low in off-set voltage is disclosed in “Electronics Letters”, Vol. 36, No.3, pp. 264-265 (2000).
As for (2), it is important to maintain a proper current gain. The power consumption of bias circuit decreases with increase of current gain of driver-stage HBT and output-stage HBT. However, the high current gain exceeding, for example, 70 to 100 causes decrease of collector-emitter breakdown voltage, resulting in lowering of reliability of power amplifiers. Therefore, about 50 is desirable as a current gain of the driver-stage HBT and the output-stage HBT.
However, in case a prior art collector top HBT (
FIG. 31
) is employed for (1), there is a problem that even if a current gain of about 50 is obtained in the case of a large area HBT of about 100×100 &mgr;m
2
in collector size, the current gain is smaller than 10 in an HBT of lower collector size used as a transistor finger of power amplifier, for example, an HBT of 2×20 &mgr;m in collector size (FIG.
32
). Thus, there is a problem that even if the power conversion efficiency of the driver-stage HBT and the output-stage HBT is improved by employing the collector top HBT, the power conversion efficiency of the whole power amplifier is not improved as a result of increase of the power consumption of bias circuit.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to diminish the dependence of current gain in collector top HBT on the size of collector.
The above object can be attained in the following manner. That is, the base layer of collector top heterojunction bipolar transistor is disposed not so as to cover the whole high resistance extrinsic emitter area, and the base electrode is allowed to be present on the high resistance extrinsic emitter area and electrically connected to the side face of the base layer.
Furthermore, the above object can be attained by the method for producing a collector top heterojunction bipolar transistor which comprises a step of growing an emitter layer comprising an n-type compound semiconductor on a single crystal semiconductor substrate, a step of growing on the emitter layer a base layer comprising a p-type compound semiconductor having a forbidden band width smaller than that of the compound semiconductor constituting the emitter layer, a step of processing the base layer into a desired shape, and a step of forming by ion implantation a high resistance extrinsic emitter area on the area of the emitter layer which is not covered with the base layer.
REFERENCES:
patent: 5289020 (1994-02-01), Hirose et al.
patent: 5757039 (1998-05-01), Delaney et al.
patent: 10-135750 (1998-05-01), None
Mochizuki, R. J. et al, “GaInP/GaAs collector-up tunnelling-collector heterojunction bipolar transistors with zero-offset and low-knee-voltage characteristics”,Electronics Letters, vol. 36, Feb. 3, 2000, pp. 264-265.
Mochizuki et al. ;GaInP/GaAs . . . (C-Up TC-HBTs): Optimization of Fabrication Process and Epitaxial Layer Structure for High-Efficiency High-Power Amplifiers, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2277-2283.
Mochizuki Kazuhiro
Ohbu Isao
Oka Tohru
Yamashita Kiichi
Lattin Christopher
Miles & Stockbridge P.C.
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