Semiconductor device and method of producing the same

Details Semiconductor device and method of producing the same Semiconductor device and method of producing the same

1998-10-26

2001-01-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S780000, C438S781000, C438S790000

Reexamination Certificate

active

06171979

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device comprising an interlaminar insulating layer disposed on a wiring layer and composed of a porous layer or an SOG layer, and a method of producing the same.
As examples of the material forming an interlaminar insulating layer in a semiconductor device, there have conventionally been known organic and inorganic materials. An interlaminar insulating layer formed of an organic material is disadvantageously poor in heat resistance although its relative dielectric constant is relatively low, while an interlaminar insulating layer made of an inorganic material is disadvantageously high in relative dielectric constant although its heat resistance is excellent.
As the interlaminar insulating layer formed of an organic material low in relative dielectric constant, there is known an aggregate layer comprising organic silanol condensate particulates each having a structure as shown in FIG.
18
. More specifically, each organic silanol condensate particulate is arranged such that silicon-alkyl group bonds (organic units) are uniformly dispersed, in the molecular level, in silicon-oxygen bonds (inorganic units) and that silanol groups (Si—OH) are present on the surface thereof. In
FIG. 18
, R is an alkyl group such as CH
3
, C
2
H
5
, C
6
H
5
or the like.
An interlaminar insulating layer of prior art is formed in the following manner. A TEOS derivative having an alkyl group as a substituent group (in which silicon-alkyl group bonds are substantially uniformly dispersed, in the molecular level, in silicon-oxygen bonds) is hydrolyzed and then dehydrated and condensed to prepare a silica sol, and the silica sol thus prepared is applied onto a semiconductor substrate and then thermally treated, thus forming an interlaminar insulating layer.
Each of the organic silanol condensate particulates forming an insulating layer composed of an SOG layer of prior art is arranged, as mentioned above, such that silicon-alkyl group bonds (organic units) are uniformly dispersed, in the molecular level, in silicon-oxygen bonds (inorganic units), and the silicon-alkyl group bonds are less stable than the silicon-oxygen bonds. Therefore, a variety of problems arise as set forth below. However, the following description will first discuss, as a premise, a process of forming a contact hole in an insulating layer composed of an SOG layer formed on a semiconductor substrate having a metallic layer.
As shown in FIG.
19
(
a
), the first layer of SiO,
102
having a thickness of 50 nm is deposited, by a CVD method, throughout the surface of the first metallic wiring layer of aluminium
101
formed on a semiconductor substrate
100
. After an interlaminar insulating layer
103
composed of an SOG layer is deposited on the first layer of SiO
2
102
, the second layer of SiO
2
104
having a thickness of 100 nm is deposited on the interlaminar insulating layer
103
by a CVD method as shown in FIG.
19
(
b
).
Then, a resist pattern
105
composed of organic matter is formed on the second layer of SiO
2
104
as shown in FIG.
19
(
c
). Then, using the resist pattern
105
, the first layer of SiO
2
102
, the interlaminar insulating layer
103
and the second layer of SiO
2
104
are etched to form a contact hole
106
as shown in FIG.
20
(
a
).
As shown in FIG.
20
(
b
), the resist pattern
105
is then removed using oxygen plasma.
As mentioned earlier, the silicon-alkyl group bonds are less stable than the silicon-oxygen bonds. Accordingly, oxidative decomposition of the silicon-alkyl group bonds proceeds deep in the lateral wall of the contact hole
106
in the interlaminar insulating layer
103
. Side-etching disadvantageously occurs in those portions of the interlaminar insulating layer
103
exposed to the contact hole
106
as shown in FIG.
20
(
b
).
Due to the heat from a surface thermal treatment conducted just before the second layer of metallic wiring
107
is embedded in the contact hole
106
(See FIG.
21
), moisture is generated from the interlaminar insulating layer
103
as shown in FIG.
20
(
c
). Disadvantageously, the interlaminar insulating layer
103
absorbs moisture to increase the dielectric constant, and the surface of the first metallic wiring layer of aluminium
101
is oxidized to increase the contact resistance.
When the second layer of metallic wiring
107
is deposited as shown in
FIG. 21
, a void
108
is generated in the second layer of metallic wiring
107
due to the side-etching above-mentioned. This disadvantageously causes the second layer of metallic wiring
107
to be reduced in thickness or to be disconnected.
There is desired an interlaminar insulating layer low in relative dielectric constant yet assuring the heat resistance. In this connection, the following technique is proposed to form cm interlaminar insulating layer composed of a porous layer.
FIG. 22
shows a sectional structure of a semiconductor device disclosed by Japanese Patent Publication No. 7-46698. As shown in
FIG. 22
, a metallic wiring
111
is formed on a semiconductor substrate
110
and an interlaminar insulating layer
112
composed of a porous layer is formed throughout the surface of the semiconductor substrate
110
including the metallic wiring
111
.
FIG. 23
shows a sectional structure of a semiconductor device disclosed by Japanese Patent Publication No. 6-12790. As shown in
FIG. 23
, a metallic wiring
121
is formed on a semiconductor substrate
120
and a first SOG layer
122
is formed, by a CVD method, throughout the surface of the semiconductor substrate
120
including the metallic wiring
121
. Then, an organic porous layer
123
is formed on the first SOG layer
122
, and a second SOG layer
124
is then formed on the porous layer
123
by a CVD method. These first SOG layer
122
, the organic porous layer
123
and the second SOG layer
124
form an interlaminar insulating layer.
In any of the publications above-mentioned, however, no particular description has been made of how to form the porous layer. Accordingly, porous layer forming methods discussed in the following papers are now taken into consideration.
As a first porous layer forming method, there is mentioned a method disclosed by IEEE Transactions on components, hybrids, and manufacturing technology, Vol. 15, No. 6 p. 925 (1992). More specifically, there is formed an organic high polymer layer composed of a co-polymer comprising an organic high polymer precursor high in heat resistance and an organic high polymer precursor low in heat resistance, and the organic high polymer layer thus formed is then thermally treated to decompose the organic portion low in heat resistance, thus forming a porous layer composed of an organic high polymer material.
As a second porous layer forming method, there is mentioned a method disclosed by Makromol. Chem., Macromol. Symp. 42/43, 393 (1991). More specifically, a silica film containing an organic high polymer is formed from a mixture solution of a silanol sol and an organic high polymer, and then thermally treated to pyrolytically decompose the organic high polymer, thus forming a porous layer composed of an inorganic material.
However, when forming an embedded wiring in an interlaminar insulating layer composed of a porous layer, the following problem arises. When a concave groove for an embedded wiring is formed in the interlaminar insulating layer composed of a porous layer and a wiring material is embedded in the concave groove thus formed, the wiring material enters holes in the porous layer. This disadvantageously deteriorates the insulating properties of the interlaminar insulating layer composed of a porous layer. Further, the wiring layer becomes uneven at the lateral side thereof to deteriorate the resistance to electromigration of the wiring layer. This disadvantageously deteriorates the stability of electric characteristics of the semiconductor device. It is therefore difficult to form an embedded wiring in the interlaminar insulating layer composed of a porous layer.
According to the first po

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