Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2008-12-10
2010-02-23
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S109000, C438S111000, C438S113000, C438S118000, C438S123000, C438S125000, C257SE21503
Reexamination Certificate
active
07666709
ABSTRACT:
A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.
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patent: 6759277 (2004-07-01), Flores et al.
patent: 7189593 (2007-03-01), Lee
patent: 2006/0255458 (2006-11-01), Dangelmaier
patent: 2008/0029890 (2008-02-01), Cheng
Goh Hin Hwa
Huang Rui
Lin Yaojian
Atkins Robert D.
Lee Kyoung
Richards N Drew
STATS ChipPAC Ltd.
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