Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2010-03-09
2011-11-01
Nguyen, Thinh T (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S405000, C438S149000, C257S347000, C257S348000
Reexamination Certificate
active
08048759
ABSTRACT:
The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.
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patent: 7173319 (2007-02-01), Iwamatsu et al.
patent: 2002/0123205 (2002-09-01), Iwamatsu et al.
patent: 2005-19996 (2005-01-01), None
Nguyen Thinh T
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Renesas Electronics Corporation
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