Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2005-08-02

2008-03-25

Nguyen, Van Thu (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000

Reexamination Certificate

active

07348625

ABSTRACT:
An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

REFERENCES:
patent: 6727136 (2004-04-01), Buller et al.
patent: 6737324 (2004-05-01), Chang
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patent: 6878988 (2005-04-01), Lee et al.
patent: 7015540 (2006-03-01), Ishii et al.
patent: 2005/0051832 (2005-03-01), Fukumura et al.
Y. Sasago et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10MB/s,” IEEE, 2003, pp. 34.2.1-34.2.4.

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