Semiconductor device and method of manufacturing the same

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S406000, C438S455000, C438S503000, C257SE29193, C257SE29122, C257SE21567, C257SE21569

Reexamination Certificate

active

11064943

ABSTRACT:
A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.

REFERENCES:
patent: 4948748 (1990-08-01), Kitahara et al.
patent: 4985745 (1991-01-01), Kitahara et al.
patent: 5079183 (1992-01-01), Maeda et al.
patent: 5399507 (1995-03-01), Sun
patent: 5476809 (1995-12-01), Kobayashi
patent: 5728623 (1998-03-01), Mori
patent: 5740099 (1998-04-01), Tanigawa
patent: 6690043 (2004-02-01), Usuda et al.
patent: 6767802 (2004-07-01), Maa et al.
patent: 2001/0008292 (2001-07-01), Leobandung et al.
patent: 2002/0127816 (2002-09-01), Cha et al.
patent: 2003/0104658 (2003-06-01), Furukawa et al.
patent: 2005/0070070 (2005-03-01), Rim
patent: 4-372166 (1992-12-01), None
patent: 9-219524 (1997-08-01), None
patent: 11-204541 (1999-07-01), None
patent: 11-340337 (1999-12-01), None
patent: 2000-277715 (2000-10-01), None
patent: 2001-44425 (2001-02-01), None
patent: 2002-270826 (2002-09-01), None
patent: 2003-318110 (2003-11-01), None
J. Welser et al., “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs”, IEDM 94, pp. 373-376, (1994).
T. Mizuno et al., “High Performance CMOS Operation of Strained-SOI MOSFETs using Thin Film SIGe-on-Insulator Substrate,” 2002 Symposium on VLSI Technology Digest of Technical Papers (2002).
Copy of Notification of Reasons for Rejection issued by the Japanese Patent Office dated Mar. 14, 2006, and English translation thereof.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3822471

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.