Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2007-04-03
2007-04-03
Doan, Theresa T. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S784000, C257S786000
Reexamination Certificate
active
10397278
ABSTRACT:
A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads11as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes12for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines13for connecting the plurality of pads11to the plurality of contact holes12correspondingly. In this case, the layout of the plurality of pads is made common regardless of the type of product.
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patent: 6670700 (2003-12-01), Hashimoto
Crowell & Moring LLP
Doan Theresa T.
UMC Japan
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