Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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C257S784000, C257S786000

Reexamination Certificate

active

10397278

ABSTRACT:
A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads11as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes12for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines13for connecting the plurality of pads11to the plurality of contact holes12correspondingly. In this case, the layout of the plurality of pads is made common regardless of the type of product.

REFERENCES:
patent: 5205036 (1993-04-01), Yamazaki
patent: 5444303 (1995-08-01), Greenwood et al.
patent: 5691568 (1997-11-01), Chou et al.
patent: 6344696 (2002-02-01), Nakamura et al.
patent: 6501169 (2002-12-01), Aoki et al.
patent: 6512298 (2003-01-01), Sahara et al.
patent: 6670700 (2003-12-01), Hashimoto

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