Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-08-22
2006-08-22
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S162000, C438S528000
Reexamination Certificate
active
07094663
ABSTRACT:
The semiconductor device has a low-resistance layer provided under the interconnection extending from the signal input to a gate of MOSFET. The low-resistance layer decreases the substrate resistance and the noise characteristic of the semiconductor device can also be improved. The low-resistance layer can be provided on a surface of the substrate or a polysilicon interconnection.
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Kabushiki Kaisha Toshiba
Lindsay Jr. Walter L.
Pillsbury Winthrop Shaw & Pittman LLP
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