Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S761000, C257S750000, C257S751000, C257S760000, C257S762000, C257S759000, C257S639000, C257S640000, C438S639000, C438S640000

Reexamination Certificate

active

07057286

ABSTRACT:
A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

REFERENCES:
patent: 6140226 (2000-10-01), Grill et al.
patent: 6225207 (2001-05-01), Parikh
patent: 6514852 (2003-02-01), Usami

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