Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-02
2004-10-05
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S900000, C257S411000, C257S410000, C257S406000, C257S405000, C257S404000, C257S393000, C257S392000, C257S389000, C257S387000, C257S399000, C257S256000, C438S184000, C438S230000, C438S265000, C438S303000, C438S216000, C438S288000
Reexamination Certificate
active
06800909
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Applications No. 2001-308429 filed in Oct. 4, 2001, and No. 2002-256229, filed in Aug. 30, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having one conductivity type impurity regions, that are formed in vicinity of two opposite conductivity type impurity diffusion regions constituting the source/drain in one conductivity type substrate respectively by the pocket injection technology, and a method of manufacturing the same.
2. Description of the Prior Art
The MOS transistor is designed based on the scaling theory. If the MOS transistor whose gate length is less than 50 nm is fabricated based on this theory, the short channel effect is generated. In order to suppress such short channel effect, for instance, the technology of increasing the n-type impurity concentration in vicinity of top ends of the n-type impurity diffusion regions serving as the source/drain in the p-type silicon substrate rather than the p-type impurity concentration of the channel region, i.e., the pocket injection technology, is being watched with interest.
Then, the application of the pocket injection technology to the steps of forming the MOS transistor will be explained hereunder.
First, as shown in
FIG. 1A
, the gate electrode
103
is formed on the p-type silicon substrate
101
via the gate insulating film
102
. This gate electrode
103
has such a structure that the notch (pitch)
103
a
is formed at its lower portion, and is called the notch-type gate electrode. In
FIG. 1A
, a reference
106
denotes the device isolation STI (shallow trench isolation) formed in the silicon substrate
101
.
Then, as shown in
FIG. 1B
, the p-type impurity is ion-implanted into the silicon substrate
101
in the oblique direction to the substrate surface. Thus, the p-type pocket regions
101
a
whose p-type impurity concentration is higher than the channel region are formed on both sides of the gate electrode
103
in the p-type silicon substrate
101
. A distance between end portions of two p-type pocket regions
101
a
is shorter than a width (gate length) of the gate electrode
103
at the lower portion of the gate electrode
103
and also the p-type pocket regions
101
a
are formed away from the surface of the silicon substrate
101
.
Then, as shown in
FIG. 1C
, the n-type impurity regions (extension regions)
104
a
are formed on both sides of the gate electrode
103
by ion-implanting the n-type impurity in the direction substantially perpendicular to the p-type silicon substrate
101
while using the gate electrode
103
as a mask.
Then, as shown in
FIG. 1D
, the insulating film is formed on the silicon substrate
101
and the gate electrode
103
by the CVD method. Then, the sidewall spacers
105
are left on the side surfaces of the gate electrode
103
by isotropic-etching the insulating film in the vertical direction. Then, the n-type impurity regions
104
b
of high concentration are formed on both sides of the gate electrode
103
by ion-implanting the n-type impurity into the silicon substrate
101
while using the gate electrode
103
and the sidewall spacers
105
as a mask.
The n-type impurity diffusion regions
104
serving as the source/drain and having the LDD structure are constructed by the n-type impurity diffusion regions
104
a
,
104
b
that are formed by executing twice the ion implantation as described above, respectively. The p-type pocket regions
101
a
are jointed to lower portions of the end portions of the n-type impurity diffusion regions
104
.
Accordingly, the channel region that is formed in vicinity of the gate electrode
103
and the p-type pocket regions
101
a
whose p-type impurity concentration is higher than the channel region are present between two n-type impurity diffusion regions
104
.
With the above, the n-type MOS transistor is formed on the silicon layer
101
. In this case, if the p-type MOS transistor is to be formed, the silicon substrate is set to the n-type, and the impurity that is ion-implanted to form the pocket regions is set to the n-type, and the impurity that is ion-implanted to form the source/drain is set to the p-type.
After such MOS transistor is formed, although not shown, the suicide layer is formed on the silicon substrate
101
and the gate electrode
103
, then the interlayer insulating film for covering the MOS transistor is formed on the silicon substrate
101
, and then the multi-layered wiring structure, etc. are formed on the interlayer insulating film. But their details are omitted.
The pocket injection technology that employs the notch-type gate electrode as described above is set forth in S.Piddin et.al, Symp. VLSI tec. 2001 p.35, for example.
Meanwhile, it will be explained hereunder which pocket is formed if the pocket is formed by using the normal gate electrode having no notch portion
103
a.
First, as shown in
FIG. 2A
, in the situation that the gate electrode
111
whose cross section is formed as a rectangle is formed on the silicon substrate
101
via the gate insulating film
102
, the p-type impurity having the same conductivity type as the silicon substrate
101
is ion-implanted (I.I) in the oblique direction to the substrate surface. In this case, since the distribution of the thickness of the gate electrode
111
is generated along the ion implantation direction of the p-type impurity, the corners of the lower portions of the gate electrode
111
are mostly reduced in thickness.
Therefore, as shown in
FIG. 2B
, the p-type impurity that is obliquely ion-implanted into the surface of the silicon substrate
101
exists at an almost uniform depth in the portion, in which the gate electrode
111
is not formed, out of the silicon substrate
101
. However, the energy of the p-type impurity that has passed through the corners of the lower portions of the gate electrode
111
is attenuated, and thus shallow peaks are present in the silicon substrate
101
. Also, the impurity that is ion-implanted via the thick portions of the gate electrode
111
is absorbed in the gate electrode
111
and does not come up to the inside of the silicon substrate
101
. Accordingly, the p-type impurity high concentration region
101
a
has the distribution of the concentration peak such that, as shown in
FIG. 2B
, the concentration peak is shallow under the gate electrode
111
but is deep on both sides of the gate electrode
111
.
The high concentration profile of the p-type impurity when the p-type impurity is ion-implanted into the n-type substrate
101
, on which the gate electrode
111
without the notch is formed, in the oblique direction from the normal is shown in FIG.
3
. In
FIG. 3
, as illustrated in the area encircled by a broken line, the regions in which the p-type impurity concentration is higher than the original concentration are present in the channel region in vicinity of the surface of the silicon substrate
101
. In this case, the black portions in
FIG. 3
denote the portion whose p-type impurity concentration is higher than the channel region.
In this manner, if the pocket portions
101
a
have the concentration distribution close to the channel region under the gate electrode
111
such distribution interferes with the increase of the ON-current and thus the increase in the circuit speed becomes difficult.
In contrast, if the notch-type gate electrode
103
shown in
FIG. 1A
is employed, the impurity that is obliquely ion-implanted (I.I) through the notch portion
103
a
of the gate electrode
103
can be injected deeply, as shown in
FIG. 4A
, like the region in which the gate electrode
103
is not present. Also, when the ions that are obliquely implanted into the gate electrode
103
serving as the visor on the notch portion
103
a
are passed through the gate electrode
103
, a part of such ions l
Fujita Tohru
Kokura Hikaru
Matsunaga Daisuke
Sugatani Shinji
Sugiyama Koichi
Fujitsu Limited
Im Junghwa M.
Westerman Hattori Daniels & Adrian LLP
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