Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-12
2004-11-09
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C438S217000
Reexamination Certificate
active
06815773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor having an SOI (silicon on insulator) structure and a method of manufacturing the same, and more specifically to a method of manufacturing a transistor having a SOI structure in which a buried insulating film can be increased in thickness with satisfactory controllability, and a parasitic capacitance between a drain and a supporting substrate is reduced and also, a high concentration impurity diffusion region is formed in the supporting substrate region below a low concentration drain region, thereby being capable of dealing with an increase in the withstand voltage of the transistor and high-speed operation.
2. Description of the Related Art
In a conventional semiconductor device with an SOI structure, an SOI substrate is used, and thus, a field insulating film and a buried insulating film contact with each other to attain electrically complete separation. Therefore, the semiconductor device is soft error-free and latchup-free. Further, a parasitic capacitance is reduced by using the SOI substrate, and thus, a high-speed IC can be realized. Moreover, the semiconductor device has an advantage that improvement in transistor characteristics enables a low-power-consumption IC and other advantages.
The conventional semiconductor device that employs an SOI substrate has many advantages, including high speed operation, low power consumption, being free of soft errors, and being latchup-free as compared with a conventional semiconductor device that employs a bulk silicon substrate, but has a problem in that the withstand voltage thereof is reduced due to a high electric field generated in a surface in the vicinity of a drain below a gate, similarly to the conventional semiconductor device that employs a silicon substrate.
SUMMARY OF THE INVENTION
In order to obtain a structure for relaxing an electric field at a drain end, according to an aspect of the present invention, there is provided a manufacturing method comprising the steps of forming a mask film on a region which corresponds to a channel region and a low concentration drain region of a transistor which are formed later, in a surface of an SOI substrate with the use of the SOI substrate, implanting oxygen ions into the surface of the SOI substrate to locate peaks of an impurity concentration in an upper portion and a lower portion of a buried insulating film performing heat treatment on the SOI substrate that has been implanted with oxygen ions to form a buried insulating film having a thin portion corresponding to the channel region and the low concentration drain region and thick portions corresponding to other portions, and implanting impurity ions into a supporting substrate region below the low concentration drain region to form a high concentration impurity diffusion layer.
REFERENCES:
patent: 5138409 (1992-08-01), Kawai
patent: 5359219 (1994-10-01), Hwang
Osanai Jun
Uehara Osamu
Adams & Wilks
Crane Sara
Seiko Instruments Inc.
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