Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-10
2004-10-19
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S900000
Reexamination Certificate
active
06806540
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-310155, filed Oct. 11, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a high voltage transistor, particularly, to a semiconductor device having a high degree of integration and a method of manufacturing the same.
2. Description of the Related Art
The construction of a conventional nonvolatile semiconductor memory device will now be described with reference to
FIGS. 21 and 22
.
FIG. 21
is a cross sectional view showing the construction of the cell portion and the peripheral circuit portion of a NOR type flash memory.
As shown in
FIG. 21
, the NOR type flash memory comprises a high voltage transistor
203
used for writing, reading and erasing information in a memory cell
202
and a low voltage transistor
204
in addition to the memory cell
202
formed of a stacked transistor including a stacked gate structure having a floating gate
200
having a memory retaining capability and a control gate
201
.
The memory cell
202
is constructed such that a gate structure is interposed between source/drain diffusion layers
214
. The gate structure has a stacked gate structure including a tunnel oxide film
218
formed on a semiconductor substrate
223
, the floating gate
200
formed on the tunnel oxide film
218
, an interlayer insulating film
219
formed on the floating gate
200
, and the control gate
201
formed on the interlayer insulating film
219
. Further, a gate side wall
209
b
is formed in a manner to surround the stacked gate structure noted above. Incidentally, the memory cell
202
is separated from the memory peripheral element such as a high voltage transistor by a shallow trench isolation layer
221
.
The high voltage transistor
203
is constructed such that a gate structure is interposed between two N
−
type diffusion layers
206
formed in the surface region of the substrate
223
. The gate structure noted above includes a thick gate oxide film
205
formed on the semiconductor substrate
223
and a gate electrode
211
formed on the gate oxide film
205
. A gate side wall
209
equal in thickness to the gate side wall
209
b
of the memory cell
202
is formed to surround the gate structure, and the surface region of the N
−
diffusion layer
206
is covered with the gate insulating film
205
and the gate side wall
209
. Further, N
+
diffusion layers
207
are formed to extend away from the gate structure on those portions of the surface of the substrate
223
which are positioned outside the N
−
diffusion layers
206
.
Further, the low voltage transistor
204
referred to previously is formed away from the high voltage transistor
203
, with a shallow trench isolation layer
221
interposed therebetween. In the low voltage transistor
204
, a gate electrode is formed between adjacent N
−
diffusion layers
216
. The gate structure comprises a thin gate oxide film
220
formed on the semiconductor substrate
223
and a gate electrode
212
formed on the gate oxide film
220
. A side wall
209
a
equal in thickness to the memory cell
202
is formed to surround the gate structure of the transistor
204
. Further, N
+
diffusion layers
215
are formed to extend from the N
−
diffusion layers
216
to the outside of the gate structure.
The high voltage transistor
203
is used for supplying a high voltage of ten and several volts to the memory cell
202
for the operation of, for example, writing and erasing information. In the high voltage transistor
203
, the gate oxide film
205
has a large thickness, e.g., 20 nm, in order to prevent the gate oxide film
205
from being subjected to the insulation breakdown under a high voltage. In addition, it is necessary to set the junction breakdown voltage of the source/drain diffusion layers
206
and
207
at a high value of ten and several volts.
Under the circumstances, the diffusion layer
206
having a low concentration of N-type (P-type) impurity is formed deep. At the same time, a distance
208
(hereinafter referred to as an LDD length
208
) of the tip of the diffusion layer
206
having a low concentration of the N-type (P-type) impurity, the tip being positioned below the gate insulating film
205
and the gate side wall
209
, from the boundary between the diffusion layer
207
having a high concentration of an N-type (P-type) impurity and the diffusion layer
206
having a low impurity concentration noted above is set at a large value so as to facilitate the expansion of the depletion layer within the diffusion layer
206
having a low impurity concentration, thereby increasing the junction breakdown voltage.
Particularly, in the case of the high voltage transistor
203
is of a PMOS transistor, a P-type impurity of boron tends to be diffused into the semiconductor substrate
223
by the various heating steps employed in the process between the formation of the diffusion layers
206
,
207
and the completion of the semiconductor device. Therefore, unless the thickness of the gate side wall
209
determining the LDD length
208
is maintained at a level not lower than a certain level, the LDD length
208
of the low impurity concentration region
206
positioned below the gate insulating film
205
and the gate side wall
209
is shortened or tends to be eliminated by the diffusion of boron from the high impurity concentration region
207
into the low impurity concentration region
206
.
On the other hand, in a high voltage NMOS transistor (not shown), an N-type impurity of arsenic has a degree of diffusion in the heating step lower than that of the P-type impurity of boron so as to make it possible to form the gate side wall in a thickness smaller than that for the PMOS transistor
203
.
However, in the conventional LDD structure shown in
FIG. 21
, the gate side wall
209
has a large thickness, e.g., 0.2 &mgr;m. The thickness of the gate side wall
209
is determined to conform with the PMOS transistor
203
requiring a high breakdown voltage. It follows that the gate side walls
209
b
and
209
a
of the memory
202
and the transistor
204
have thicknesses conforming with the high voltage PMOS transistor
203
.
The ion implantation of a low concentration of a P-type impurity in the high voltage transistor
203
is performed after formation of the gate electrode
211
, followed by forming the gate side wall
209
. It is possible to set the LDD length
208
at a large value if the ion implantation of a P-type impurity is performed, after formation of the gate side wall
209
, for forming the P
+
diffusion layer
207
with the gate side wall
209
used as a mask. In the prior art, each of the side wall
209
a
of the low voltage transistor
204
and the side wall
209
b
of the memory cell
202
is formed in a large thickness of about 0.2 &mgr;m like the side wall of the high voltage transistor
203
. What should be noted is that, in the prior art, the side walls
209
b
,
209
and
209
a
of the memory cell
202
, and the transistors
203
and
204
, respectively, are uniformly formed in the same thickness so as to decrease the number of process steps by forming simultaneously the side walls of the memory cell
202
and the transistors
203
and
204
in the same manufacturing process.
It should be noted that the distance between a contact hole
210
of the memory cell
202
and the gate electrode
201
, the distance between a contact hole
210
of the transistor
203
and the gate electrode
203
, and the distance between a contact hole
210
of the of the transistor
203
and the gate electrode
212
are equal to the sum of, for example, a side wall thickness
224
of the high voltage transistor
203
and an aligning allowance
225
between the side wall
209
and the contact hole
210
. The aligning allowance is determined by the accuracy
Masuda Kazunori
Naruke Kiyomi
Watanabe Hiroshi
Fahmy Wael
Pham Hoai
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