Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-01-07
2004-04-13
Mai, Son L. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S315000, C438S128000, C438S240000, C438S257000, C365S185110, C365S185330
Reexamination Certificate
active
06720579
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2001-1613, filed on Jan. 11, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and method of manufacturing the same, and more particularly to a semiconductor device and method of manufacturing the same, which has elongated wiring of silicon material such as gate lines formed to cross with an active region in a cell area.
BACKGROUND OF THE INVENTION
In a flash memory device or a dynamic random access memory (DRAM) device, gate lines generally have elongated line shapes. Also, the gate lines are formed of silicon material having conductivity lower than that of metal material. Thus, voltages at portions, for example middle portions, of the gate lines remote from portions to which voltage is first supplied, become lower than the required voltage since the gate lines have line resistance. Accordingly, the memory device needs means to compensate for a drop in voltage in the middle portions of the gate lines. However, as the elements incorporated into a semiconductor device are integrated to a higher degree, a wiring width as well as a distance between cells becomes less and less, thereby increasing line resistance. In order to maintain voltage at all portions of the gate lines at a given level and to prevent an increased delay of the gate signal due to increased line resistance, means for restoring voltage are required. However, in most means for restoring voltage, a peripheral structure in the memory device is complicated, causing a loss of integration density. To reduce these problems, there have been proposed methods of increasing conductivity, such as forming silicon wiring of the gate lines by using a multi-layered silicon layer including a metal layer, or forming a metal silicide layer on an upper surface of each gate line as in a general flash memory device shown in
FIG. 1
to
FIG. 3
FIG. 1
is a top plan view showing a potion of a cell area of a general NAND type flash memory.
Referring now to
FIG. 1
, an isolation layer is formed on a substrate to form an active region
22
in a cell area. The active region
22
comprises a plurality of line shaped sub-regions which are defined respectively by a plurality of elongated openings or gaps of the isolation layer
23
shown in FIG.
2
. In a center portion of the cell area, a common source line
45
is disposed to cross the active region
22
. In each of upper and lower portions of the cell area divided by the common source line
45
, a plurality of gate lines comprising a ground select gate line
33
g,
a plurality of, for example 8, 16, or 32 word lines WP, and a string select gate line
33
s
are formed in order from one of both sides of the common source line
45
. Namely, two equal parts of gate lines formed in the upper and lower portion of the cell area are disposed symmetrically with respect to the common source line
45
. Thus, the common source line
45
is disposed between two ground select gate lines
33
g.
Contacts
51
, which are connected with bit lines
55
, are formed in upper and lower end portions of the cell area forming drain regions of the string select gate lines
33
s.
FIG. 2
shows a cross-section taken along line I—I in FIG.
1
and
FIG. 3
shows a cross-section taken along line II—II in FIG.
1
.
Referring to
FIG. 2
, the common source line
45
is formed on the substrate in contact a portion of the active region forming common source regions
35
s
′ of the ground select gate lines
33
g
(shown in
FIG. 1
) and a portion of the isolation layer
23
therebetween. The bit lines
55
are disposed above the common source line
45
on an interlayer insulating layer
49
.
Referring to
FIG. 3
, the active region
22
is not shown upward and downward as in
FIG. 1
, but leftward and rightward. On the active region
22
, the gate lines
33
g,
WP,
33
s
are formed to cross the active region
22
. The common source line
45
is in contact with the common source regions
35
s
′ between two ground select gate lines
33
g.
In a process of forming a cell area of a flash memory device shown in
FIG. 1
to
FIG. 3
, first an isolation insulating layer
23
is formed on a substrate
20
to define an active region by means of a general shallow trench isolation (STI) process. The active region comprises a plurality of line shaped sub-regions. Thereafter, a gate insulating layer
24
is formed in the active region. Then, a plurality of gate lines comprising string select gate lines
33
s,
a plurality of word lines WP, and ground select gate lines
33
g
are formed to cross the active region. Also, source/drain regions
35
′, are formed to be overlapped with a plurality of line shaped sub-regions of the active region by doping an impurity on exposed surface of the substrate between the gate lines. The source/drain regions
35
′, formed by general ion implantation processes of using the gate lines and spacer
37
on both side walls of the gate lines as a mask, form a dual doped structure. Namely, highly doped portions are formed in the active region of the substrate between the adjacent spacers
37
, and lightly doped portions in the active region of the substrate between the gate lines and the highly doped portions, i.e., in the active region of the substrate under the spacers
37
. Then, an interlayer insulating layer
41
is deposited and planarized. Thereafter, a groove is formed to expose the common source regions
35
s
′ between the ground select gate lines
33
g
and filled with a conductor such as a polysilicon layer to form a common source line
45
. Then, after an interlayer insulating layer
49
is formed over the resultant substrate, contact holes are formed to expose drain regions
35
d
′ of the string select gate lines
33
s,
and are then filled with a conductive layer to form bit line contacts. And then, bit lines are formed.
In order to decrease line resistance of the gate lines, a metal silicide layer containing metal such as cobalt (Co) or titanium (Ti) can be formed on upper portions of the gate lines as shown in black in FIG.
3
. At this time, the metal silicide layer is also formed on the substrate in the source/drain regions
35
′. Therefore, break down is possible due to voltage in transistor channels between the source/drain regions under the gate lines, since in a high integrated NAND type flash memory device, width of the gate lines and distance between the gate lines are very minute, for example below 0.15 &mgr;m. Particularly, in case the source/drain regions are highly doped, the transistor channels are more apt to break down since in a subsequent annealing process, the doped area is more diffused, so that the length of the transistor channels is not maintained at a proper level. In this case, a leakage of current into the substrate may also occur. Therefore, the higher the integrated degree of the elements in the memory device is, the lighter the source/drain regions have to be doped. Also, in case the silicide layer is formed in the source/drain regions, conductivity of the source/drain regions is increased, so that problems such as the break down and the current leakage become more intensified.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved semiconductor device and method of manufacturing the same, which can prevent a drop in voltage and an increased delay of gate signal due to increase of line resistance of gate lines.
It is another object of the present invention to provide an improved semiconductor device and method of manufacturing the same, which can maintain an impurity concentration or conductivity of source/drain regions in a substrate at a low level, thereby preventing break down in transistor channels and current leakage from occurring.
It is other object of the present invention to provide an improved semiconductor device and method of manufacturing the same, in which a metal silicide layer is not formed
Choi Jung-Dal
Lee Won-Hong
Park Kyu-Charn
Shin You-Cheol
Mai Son L.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tran Mai-Huong
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