Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-08-25
2004-01-20
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S158000, C438S164000, C438S486000, C438S713000, C438S766000
Reexamination Certificate
active
06680223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a semiconductor thin film having a crystalline structure. Particularly, the present invention relates to a structure of an inverted stagger type thin film transistor (hereinafter abbreviated as a TFT). Moreover, the present invention relates to a structure of a semiconductor circuit, an electrooptical device, and an electronic equipment, each using the foregoing TFT.
Incidentally, in the present specification, the term “semiconductor device” indicates any device capable of functioning by using semiconductor characteristics. Any of TFTs, semiconductor circuits, electrooptical devices, and electronic equipments set forth in the present specification are contained in the category of the semiconductor device.
2. Description of the Related Art
Conventionally, a TFT is used as a switching element of an active matrix type liquid crystal display device (hereinafter abbreviated as AMLCD). At present, a market is occupied by products in which a circuit is constituted by TFTs each using an amorphous silicon film as an active layer. Particularly, as the structure of a TFT, an inverted stagger structure manufactured through simple steps is often adopted.
However, the performance of an AMLCD has been improved every year, and the operation performance (especially, operation speed) required for a TFT tends to become high. Thus, it becomes difficult to obtain an element having sufficient performance through the operation speed of a TFT using an amorphous silicon film.
Then a TFT using a polycrystalline silicon film (polysilicon film) instead of an amorphous silicon film has come into the limelight and the TFT having an active layer of the polycrystalline silicon film has been rapidly developed. At present, such TFTs have been partially made into products.
There are many publications as to the structure of an inverted stagger type TFT using a polycrystalline silicon film as an active layer. For example, there is a report “Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method: H. Hayashi et al., IEDM95, pp829-832, 1995”, the disclosure of which is herein incorporated by reference, and the like.
Although the above report explains a typical example (
FIG. 4
) of an inverted stagger structure using a polycrystalline silicon film, the reverse stagger structure (so-called channel stop type) of such a structure has various problems.
First, since the entire of an active layer is as very thin as about 50 nm, impact ionization occurs in a contact portion between a channel formation region and a drain region, so that deterioration phenomena such as hot carrier injection strikingly appear. Thus, it becomes necessary to form a large LDD region (Light Doped Drain region).
The control of the LDD region becomes the most important problem. In the LDD region, the control of the concentration of impurities and the length of the region are very delicate, and especially, the control of the length becomes a problem. At the present circumstances, although a system in which the length of the LDD region is regulated by a mask pattern is adopted, if the degree of fineness is progressed, a slight patterning error causes a large difference in TFT characteristics.
The dispersion of sheet resistance of the LDD region due to the dispersion of the film thickness of an active layer also becomes a serious problem. Moreover, the dispersion in taper angles and the like of a gate electrode also may cause the dispersion of effects of the LDD region.
Further, a patterning step is required to form the LDD region, which directly causes manufacturing steps to increase and throughput to lower. According to the reverse stagger structure set forth in the above-mentioned report, it is expected that at least six masks (until formation of source/drain electrodes) are required.
As described above, in the reverse stagger structure of the channel stop type, the LDD regions must be formed at both sides of a channel formation region in a plane in a lateral direction, so that it is very difficult to form the LDD regions with reproducibility.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique for manufacturing a semiconductor device with high mass productivity, high reliability, and high reproducibility by very simple manufacturing steps.
According to an aspect of the present invention, a semiconductor device comprising a source region, a drain region, and a channel formation region, each being made of a semiconductor layer with crystal structure, wherein each of the source region and the drain region includes a lamination structure made of, toward a gate insulating film, at least a first conductive layer, a second conductive layer having higher resistance than the first conductive layer, and a semiconductor layer having the same conductivity as the channel formation region.
According to another aspect of the present invention, in the foregoing structure of the invention, a concentration profile of impurities contained in the first and second conductive layers is continuously changed from the first conductive layer to the second conductive layer.
According to still another aspect of the present invention, in the foregoing structure, the second conductive layer includes impurities with a concentration which continuously changes within a range of 5×10
17
to 1×10
19
atoms/cm
3
.
According to still another aspect of the present invention, in the foregoing structure, two offset regions having different thicknesses exist between the channel formation region and the second conductive layer.
According to still another aspect of the present invention, in the foregoing structure, an offset region having a thickness larger than the channel formation region exists between the channel formation region and the second conductive layer.
According to still another aspect of the present invention, a semiconductor device comprises a gate electrode formed on a substrate having an insulating surface; a source region, a drain region, and a channel formation region, each being made of a semiconductor layer with crystal structure; and a source electrode and a drain electrode formed on the source region and the drain region, respectively, wherein each of the source region and the drain region includes a lamination structure made of, toward a gate insulating film, at least a first conductive layer, a second conductive layer having higher resistance than the first conductive layer, and a semiconductor layer having the same conductivity as the channel formation region; and the source electrode and/or drain electrode overlaps with the gate electrode at a portion over the channel formation region.
According to still another aspect of the present invention, a semiconductor device comprises a source region, a drain region, and a channel formation region, each being made of a semiconductor layer with crystal structure, wherein each of the source region and the drain region includes a lamination structure made of at least, toward a gate insulating film, a first conductive layer, a second conductive layer having higher resistance than the first conductive layer, and a semiconductor layer having the same conductivity as the channel formation region; and two offset regions having different film thicknesses and an HRD structure made of the second conductive layer exist between the channel formation region and the first conductive layer.
One of the two offset regions having different thicknesses is an offset in a film surface direction composed of a semiconductor layer having the same conductivity and the same thickness as the channel formation region, and the other is an offset in a thickness direction composed of a semiconductor layer having the same conductivity as the channel formation region and a film thickness larger than the channel formation region.
According to still another aspect of the present invention, a method of man
Fukunaga Takeshi
Koyama Jun
Yamazaki Shunpei
Cao Phat X.
Doan Theresa T.
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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