Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Physical deformation
Reexamination Certificate
2001-03-30
2004-07-06
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Physical deformation
C257S782000
Reexamination Certificate
active
06759722
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor element is secured to a board and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
Conventionally, semiconductor element chips (semiconductor elements; hereinafter, “chips”) have been developed incorporating integrating transistors and an IC (integrated circuit) or LSI (large-scale integration) circuit.
The chip, when applied in a semiconductor device, is typically secured to a board and then sealed in a plastic package or the like, so as to provide protection to the chip from its external environment and allow easy handling of the chip during use.
An example is taken here to describe an arrangement of a packaged semiconductor device having a chip with a transistor-integrated circuit (integrated circuit).
FIG. 19
is an explanatory drawing showing a conventional arrangement of a packaged semiconductor device
101
. The semiconductor device
101
is of a flipped-chip mounting type wherein the chip
102
is positioned so that its front faces the board
103
. A package
108
made of epoxy resin is provided to cover the back of the chip
102
, thereby sealing the chip
102
.
The chip
102
is secured to the board
103
interposed by glue (anisotropic conducting glue)
105
. The board
103
is made of glass epoxy prepared by immersing epoxy resin in glass fiber.
On the front of the chip
102
is there provided a pad section
107
as well as an integrated circuit (not shown). The pad section
107
has a bump
104
to establish contact to a wire section
106
made of copper film on the board
103
.
Now, a typical method of manufacturing such a packaged semiconductor device will be described.
First, the wire section
106
with output wiring for external connection is provided on the board
103
at a position that matches the position of the pad section
107
on the chip
102
.
Then, a bump
104
is fabricated of gold on the pad section
107
of the chip
102
, followed by application of glue
105
onto the board
103
.
The board
103
and chip
102
are stacked so that the wire section
106
matches the bump
104
(pad section
107
) in position, thereby mounting the chip
102
on the board
103
.
Thereafter, the chip
102
and board
103
are compressed and secured to each other, while heating at about 200° C. The glue
105
solidifies due to the heating, securing the chip
102
onto the board
103
. The chip
102
is sealed by epoxy resin to form the package
108
.
Generally, the chip
102
has a thickness of 200 &mgr;m or more. Besides, normally, the chip
102
is secured level (flat) onto the board
103
to retain its electrical properties.
Specific examples are disclosed about this kind of method of manufacturing a semiconductor device in Japanese Laid-Open Patent Application No. 11-238750/1999 (Tokukaihei 11-238750; published on Aug. 31, 1999), Japanese Laid-Open Patent Application No. 64-15957/1989 (Tokukaisho 64-15957; published on Jan. 19, 1989), and other documents.
Tokukaihei No. 11-238750 discloses a method of manufacturing a highly reliable semiconductor device of a flipped-chip mounting type by removing residual scum from a vicinity of the pad section on the chip and improving the adherence between the pad section (metal) and the bump (metal).
Tokukaisho No. 64-15957 discloses a method of seal an NMOS type (N-type metal oxide semiconductor) element chip in a semiconductor package with a gas and liquid, whereby a mechanical pressure (stress) is applied to the chip using a gas and liquid so as to increase current flow for improved performance of the NMOS element.
Japanese Laid-Open Patent Application No. 5-93659/1993 (Tokukaihei 5-93659; published on Apr. 16, 1993) discloses a distortion sensor which works by means of a stress being applied to various kinds of resistor elements, which is a technology not directly related to semiconductor elements, but rather to Tokukaisho No. 64-15957. The distortion sensor takes advantage of a glass layer which changes its electric resistance when distorted.
Incidentally, the semiconductor device
101
of a flipped-chip mounting type of
FIG. 19
has a structure that does not readily allow observation of the integrated circuit provided on the front of the chip
102
.
In other words, as mentioned above, the board
103
is secured on the front of the chip
102
interposed by the glue
105
. Therefore, unsealing the epoxy resin package
108
covering the back of the chip
102
permits only a look at the back of the chip
102
, allowing no observation or analysis of the structure of the integrated circuit.
However, the epoxy resin forming the board
103
, the anisotropic conducting glue
105
, etc. are removable using an etchant containing fuming nitric acid or sulfuric acid, for example. Therefore, the board
103
and glue
105
can be peeled off (removed) by the use of the etchant, separating the chip
102
from all the other parts. The chip
102
, once separated, is prone to any kind of analysis; the integrated circuit on the front can be observable, and its electrical properties are measurable by directly contacting probes.
Further, the chip
102
secured level onto the board
103
in the package
108
, i.e., packaged, has a thickness of 200 &mgr;m or more. Therefore, the chip
102
continues to be level even after it is separated from the all the other parts for analysis; the integrated circuit on the chip
102
operates normally exhibiting the same electrical properties as when it is packaged.
In short, the conventional semiconductor device
101
, when the epoxy resin is peeled to separate the chip
102
from all the other parts, is highly prone to analysis on its integrated circuit and other parts due to its arrangement and package method. This gives a rise to a problem that secrets cannot be well concealed.
Here, Tokukaihei 11-238750 and Tokukaisho 64-15957 mentioned above disclose technologies to improve the performance of the chip, but completely fails to pay attention to methods prohibiting the analysis of the chip (integrated circuit). These technologies still allow separation of the chip from all the other parts for analysis of the integrated circuit or other members.
Tokukaihei 5-93659 above, relating to a distortion sensor, belongs basically to a different field of technology from the present invention and neither discloses nor suggests the protection of the chip from analysis.
SUMMARY OF THE INVENTION
The present invention has an object to offer a semiconductor device which can completely prevent analysis of the integrated circuit of the semiconductor element secured to the board, as well as a method of manufacturing such a semiconductor device, i.e., to offer a semiconductor device which ensures protection of secrets about the semiconductor element, as well as a method of manufacturing such a semiconductor device.
In order to achieve the object, a semiconductor device in accordance with the present invention includes a semiconductor element, with an integrated circuit, secured to a board, is such that the semiconductor element is secured level and specified to operate normally only when the semiconductor element is level.
According to the arrangement, the semiconductor element is specified to operate normally only when it is level. Therefore, if the semiconductor element is no longer capable of sustaining its level shape as a result of, for example, detachment of the semiconductor element from the board, the semiconductor element does not operate normally due to a resultant change and the like in its electrical properties. Thus, secrets can be concealed safely about the semiconductor element.
In order to achieve the object, a method of manufacturing a semiconductor device in accordance with the present invention includes, after securing a semiconductor element with an integrated circuit to a board so as to be level, the step of processing at least a part of a back of the semiconductor element to develop such stress that when the semiconductor element is detached from the board, at least a part thereof deform
Ban Hiroshi
Matsumoto Hironori
Nakano Akihiko
Ohmi Toshinori
Takeda Tadao
Clark S. V.
Sharp Kabushiki Kaisha
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