Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-12-28
2003-02-18
Jackson, Jerome (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S797000, C257S750000
Reexamination Certificate
active
06522003
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semi-conductor device having wirings formed on an interlayer insulating film and a method of manufacturing the same.
2. Description of the Prior Art
In addition to a demand for higher integration density, miniaturization of the device is also required in the recent semiconductor device to suppress increase in a chip area. In order to miniaturize the device, miniaturization of the resist pattern used as a patterning mask of the film is needed.
In order to miniaturize the resist pattern, some approaches are employed, e.g., the exposure light source of short wavelength is employed, the lens with large numerical aperture (NA) is employed, the ultra-resolution technology is employed, or the like.
The exposure method using the phase shift mask can be utilized as the ultra-resolution technology, but such exposure method can achieve the sufficient effect merely under the particular condition such that the modified illumination method is employed. In addition, production of the phase shift mask yields a higher cost of the device.
If the exposure light source of short wavelength is employed, not only the exposure system but also the lens, resist, etc. must be newly developed.
Accordingly, in order to miniaturize the semiconductor device, the method of improving the exposure resolution by using the lens with large numerical aperture is normally employed.
When the resist is exposed by the light, the resolution R can be given by
R=&bgr;&lgr;/NA
(1)
Where, in Eq.(1), NA is the numerical aperture of the lens, &bgr; is a constant decided depending upon process, material, etc., and &lgr; is a wavelength of the exposure light source.
The depth of focus (DOF) which is important in the lithography technology using the light can be given by
DOF=±&lgr;/2
NA
2
(2)
As evident from Eqs.(1) and (2), the lens with the larger numerical aperture brings about reduction in the depth of focus, and also the exposure light source of the shorter wavelength brings about reduction in the depth of focus.
While, since a width of the wiring is narrowed with the miniaturization of the semiconductor device, a film thickness of the wiring must be increased to suppress increase in the wiring resistance. In the DRAM, in order to keep the requisite capacitance of the cell capacitor at a predetermined value, the structure in which a height of the capacitor is increased is employed. In addition, the multi-layered wiring structure must be employed to miniaturize the semiconductor device, so that a total film thickness of the insulating films formed on the semiconductor substrate tends to increase.
As mentioned above, when the semiconductor device is miniaturized, films formed on the semiconductor substrate are thus made thicker and thus global difference in step of the chip tends to enlarge. As described above, this is contradictory to the reduction in the depth of focus when fine patterns are to be resolved.
Accordingly, in order to resolve fine patterns, an approach of reducing the global difference in step of the semiconductor device is needed.
In order to reduce the global difference in step, there is a method of planarizing the interlayer insulating film on the semiconductor substrate. There are two types of method, if roughly classified, as the planarizing method.
One method is that the insulating film formed SiO
2
, BPSG(boro-phospho-silicate-glass), etc., the insulating film formed by using HDP (high-density-plasma), or the like is formed excessively thick on the semiconductor substrate and then such insulating film is polished.
The other method is that the insulating film is formed and then the reflow of such insulating film is caused by the thermal process to planarize.
In some cases, these two types of the planarizing process can be employed in combination.
In the case that such planarizing process of the insulating film is applied to the DRAM manufacturing steps, the insulating film is planarized and then bit lines, other wirings, other patterns, etc. are formed on the insulating film. Then, such bit lines, other wirings, other patterns, etc. are covered with the overlying insulating film.
However, when the overlying insulating film covering the wirings, other patterns, etc. is planarized by the heating, the underlying insulating film is also heated at the same time to thus reflow. Therefore, a part of the wirings and the alignment-associated marks are moved or shifted from their originally intended locations.
For example, in case the wirings are moved from the original locations, such problems are caused that, as shown in
FIG. 1
, the wiring
101
formed on the underlying insulating film
100
is displaced from the contact portion
102
prepared for another wiring formed on the wiring
101
, or the wiring
101
and the contact hole
103
formed below the wiring
101
are short-circuited.
The above-mentioned movement of the wirings and the alignment marks may be considered because the non-uniform stress is applied between the wirings, the alignment marks and the insulating film.
Such movement of the wirings is ready to occur in the course wiring density area rather than the close wiring density area, and occurs more easily if the regularity of the wirings is lost.
In addition, the movement of the wirings is not caused in the area where the wiring is connected to the underlying wiring or the impurity diffusion region, but such movement of the wirings is caused in the area where the wiring is connected only to the overlying wiring. Especially a remarkable phenomenon is that, as shown in
FIG. 1
, the wiring is moved around a bent portion of the wiring
101
as an axis.
For example, such phenomenon can be illustrated by sectional shapes as follows.
First, as shown in
FIG. 2A
, a LOCOS film
112
is formed on a surface of a silicon substrate
110
except an impurity diffusion region
111
, and then an underlying wiring
114
is formed on the LOCOS film
112
. Then, a first interlayer insulating film
115
formed of BPSG so as to cover the impurity diffusion region
111
, the LOCOS film
112
, and the underlying wiring
114
is formed, and then a surface of the first interlayer insulating film
115
is planarized by the heating. Then, a first contact hole
116
and a second contact hole
117
are formed on the impurity diffusion region
111
and the underlying wiring
114
by etching a part of the first interlayer insulating film
115
respectively. Then, first to fourth overlying wirings
118
to
121
are formed on the first interlayer insulating film
115
. The impurity diffusion region
111
is connected to the second overlying wiring
119
via the first contact hole
116
, and a part of the underlying wiring
114
is connected to the third overlying wiring
120
via the second contact hole
117
.
Thereafter, as shown in
FIG. 2B
, a second interlayer insulating film
122
covering the overlying wirings
118
to
121
is formed by the CVD method on the first interlayer insulating film
115
. Subsequently, as shown in
FIG. 2C
, an upper surface of the second interlayer insulating film
122
is planarized by heating it to reflow. In this case, the first and fourth overlying wirings
118
,
121
, which are not connected to the underlying wiring or the impurity diffusion layer, out of the overlying wirings
118
to
121
formed below the second interlayer insulating film
122
are moved by the influences of the stress caused between the films, etc.
In
FIGS. 2A
to
2
C, a reference
123
denotes a trench isolation formed in the silicon substrate
111
.
In the prior art, in order to prevent such movement of the patterns such as wirings, alignment marks, etc., the design rule has been relaxed but the alignment accuracy has been made strict. However, with the request of miniaturization and higher integration density of the patterns in recent years, the movement of the patterns which are associated wi
Ikeda Toshimi
Kawabata Kuninori
Matsumiya Masato
Minami Takayoshi
Tsuboi Osamu
Armstrong Westerman & Hattori, LLP.
Cruz Lourdes
Fujitsu Limited
Jackson Jerome
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