Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-07
2003-11-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000
Reexamination Certificate
active
06649965
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2001-192825, filed in Jun. 26, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a nonvolatile memory and a method of manufacturing the same.
2. Description of the Prior Art
The flash EEPROM as the writable nonvolatile memory is important in the semiconductor device because of its convenience. As for EEPROM, a larger scale memory capacity and a lower cost in unit of bit are demanded.
In order to respond to such demands, it is important to proceed with the miniaturization of the flash memory cell. Recently it is reported that the memory cells are miniaturized by the technique of STI (Shallow Trench Isolation) to isolate the elements mutually. Such technology is set forth in Nikkei Microdevice, March 2000, pp. 82-86, for example.
The flash memory cell utilizing STI makes it possible to proceed with the miniaturization while avoiding the bird's beak problem caused when the device isolation structure formed by the LOCOS (Local Oxidation of Silicon) method in the prior art is utilized.
The flash memory cell utilizing STI may be formed by steps described in the following, for example.
First, as shown in
FIG. 1A
, a tunnel oxide film
102
, a first silicon film
103
, and a first silicon nitride film
104
are formed sequentially on a silicon substrate
101
, then a mask is formed in the region serving as the channel of the flash memory cell, and then device isolation recesses
105
for the STI are formed by etching the first silicon nitride film
104
to an upper layer portion of the silicon substrate
101
.
Then, an SiO
2
film
106
is formed in the device isolation recesses
105
and on the silicon nitride film
104
by the CVD method. Then, the SiO
2
film
106
is polished by the CMP method to remove from an upper surface of the first silicon nitride film
104
and to leave in the device isolation recesses
105
. Therefore, the device isolation recesses
105
and the SiO
2
film
106
formed therein can function as the STI.
Then, the first silicon nitride film
104
is selectively etched. Then, as shown in
FIG. 1B
, a second silicon film
107
and a second silicon nitride film
108
are formed sequentially on the SiO
2
film
106
and the first silicon film
103
. The first silicon film
103
and the second silicon film
107
are formed as a floating gate by the patterning.
Then, as shown in
FIG. 1C
, the second silicon nitride film
108
is patterned into shapes that are separated on the device isolation recesses
105
. In addition, a third silicon nitride film
109
is formed on the overall surface, and then this third silicon nitride film
109
is etched by the anisotropic etching and is left on side walls of the second silicon nitride film
108
as sidewall spacers.
Then, as shown in
FIG. 1D
, the second silicon film
107
is divided on the device isolation recesses
105
by etching the second silicon film
107
while using the patterned second and third silicon nitride films
108
,
109
as a mask.
Then, the second and third silicon nitride films
108
,
109
are removed, and then an ONO film
111
and a third silicon film
112
are formed in sequence on the overall surface. Then, the third silicon film
112
is patterned into a shape of the control gate and also the second silicon film
107
is patterned into a shape of the floating gate
110
(FIG.
1
E).
In steps described above, the reason for patterning the second silicon film
107
by using the second silicon nitride film
108
and the sidewalls formed on the side walls of the film
108
as the mask is to increase the coupling capacity between the floating gate
110
and the control gate
112
.
However, according to above-mentioned steps, the alignment of the exposure mask used to pattern the second silicon nitride film
108
on the second silicon film
107
is needed. Therefore, since the displacement margin must be assured, such margin makes it difficult to proceed the further miniaturization.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method capable of achieving the miniaturization of the memory cell rather than the prior art.
Then, advantages of the present invention will be explained hereunder.
According to the present invention, the second semiconductor film is selectively grown on the first semiconductor film being put between the device isolation insulating films in the STI structure, and also the second semiconductor film is grown to extend over the device isolation insulating film. In this case, the first semiconductor film and the second semiconductor film serve as the floating gate of the flash memory cell.
Therefore, since the area of the floating gate that overlaps with the control gate becomes wider than the area of the floating gate that contacts to the tunnel insulating film, the higher integration of the memory cell can be achieved and also the nonvolatile memory cell having the high coupling capacitance between the floating gate and the control gate can be formed.
Since the upper portion of the floating gate is shaped in a self-aligned manner, there is no need to execute the patterning using the mask and thus the problem of positional displacement does not occur. Therefore, the alignment margin can be made small by such displacement and the reduction of the cell area can be achieved.
Also, when the dielectric film is formed on the floating gate and then the film serving as the control gate is formed, the etching residue is hardly generated on the gentle curved surface of the upper surface of the control gate in patterning this film. Thus, the working can be made easy.
In addition, as the result that side portions of the upper surface of the second semiconductor film serving as the floating gate are formed as the smooth curved surface, the film thickness of the dielectric film, e.g., the ONO film, formed on the upper surface of the floating gate becomes uniform, and thus the electric field concentration applied to the dielectric film can be avoided. As a result, the insulating withstanding voltage between the control gate and the floating gate can be maintained high, and the nonvolatile memory with the higher reliability can be formed.
REFERENCES:
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6417047 (2002-07-01), Isobe
patent: 6462373 (2002-10-01), Shimizu et al.
patent: 3-44034 (1991-02-01), None
patent: 4-192422 (1992-07-01), None
patent: 10-256399 (1998-09-01), None
patent: 11-163304 (1999-06-01), None
patent: 2000-12813 (2000-01-01), None
patent: 2000-188346 (2000-07-01), None
Sugatani Shinji
Takada Kazuhiko
Ho Tu Tu
Nelms David
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