Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-04
2003-12-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000
Reexamination Certificate
active
06661052
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-267676, filed Sep. 4, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having trench type device isolation regions and a method of manufacturing the semiconductor device. More specifically, the present invention relates to the structure of trench type device isolation regions of a semiconductor device having semiconductor active regions self-aligned to electrode layers and a method of formation thereof. The present invention is applied, for example, to a nonvolatile memory having a two-layer (stacked) gate structure in which the floating gate is self-aligned to a device isolation region.
2. Description of the Related Art
As a nonvolatile semiconductor storage device that is electrically re-programmable which is adapted for high packing density and large capacity, a flash memory is well known. The flash memory has an array of memory cells of the MOS transistor structure in which two gate electrode layers are stacked; a charge storage layer (floating gate electrode) and a control gate electrode layer.
In the memory cell array of a NAND type flash memory, a plurality of memory cells are series-connected with the source of one cell used as the drain of the adjacent one, thereby forming a NAND configuration with a series of memory cells. Select transistors are placed at both ends of each NAND series. The source or drain of one select transistor is connected to a bit line through a bit line contact, while the source or drain of the other select transistor is connected to a source line through a source line contact.
In manufacturing such a NAND type flash memory, a gate preformation process may be used. This process involves forming a gate oxide over the entire surface of a silicon substrate (including the memory cell area and the peripheral circuit area), depositing a polysilicon film which will serve as floating gates of memory cells (cell transistors), patterning the deposited polysilicon film to form floating gate electrodes, and forming an insulating film for trench type device isolation regions to self-align to the floating gate electrodes.
At least part of a number of peripheral transistors that make up peripheral circuits of memory cells (for example, the select transistors) may be formed into the stacked gate structure which, like the memory cells, comprises a charge storage layer and a control gate layer. In this case, the gates of transistors of the same gate structure in the memory cell area and the peripheral circuit area can be processed under the same etching conditions, allowing the processing steps to be reduced and the processing processes to be made common to each other.
FIGS. 18A
,
18
B and
18
C are sectional views, at a stage of manufacture, of a conventional NAND type flash memory. More specifically,
FIGS. 18A and 18B
are sectional views of the stacked gate structure of memory cells in the direction of gate width W (in the direction of word lines) and in the direction of gate length L, respectively, and
FIG. 18B
is a sectional view of a peripheral transistor in the direction of gate length L.
FIGS. 19A
,
19
B and
19
C through
FIGS. 22A
,
22
B and
22
C are sectional views, at subsequent stages of manufacture, of the same portions of the conventional NAND type flash memory as in
FIGS. 18A
,
18
B and
18
C, respectively.
First, as shown in
FIGS. 18A
,
18
B and
18
C, a first insulating film
11
is formed over the entire surface of a semiconductor substrate (Si substrate)
10
. A first layer
13
a
(lower layer) of polysilicon for floating gate electrode is then formed on the first insulating film
11
.
Next, device isolation trenches are formed to self-align to the floating gate electrodes
13
a
and an insulating film is deposited to fill the device isolation trenches. After that, the deposited insulating film is smoothed until the surface of the first floating gate electrode layer
13
a
is exposed, thereby forming device isolation regions
30
. In this case, the top of the device isolation regions
30
is at a level above the Si substrate surface. That is, a step exists between the top of the device isolation region
30
and the Si substrate surface.
Next, a floating gate electrode layer
13
b
as a second layer consisting of polysilicon is formed over the entire surface and then patterned by means of lithographic and etching techniques. In this case, the second floating gate electrode layer
13
b
is stacked on the first floating gate electrode layer
13
a
and patterned to overlap the device isolation regions
30
.
Next, a second insulating film
12
is formed over the entire surface of the substrate. A control gate electrode layer
14
is formed on the second insulating film
12
and then formed on top with a gate masking material layer
31
.
Next, as shown in
FIGS. 19A
,
19
B and
19
C, the gate masking material layer
31
is patterned to form a gate masking pattern
31
.
Next, as shown in
FIGS. 20A
,
20
B and
20
C, the control gate electrode layer
14
is etched using the gate masking pattern
31
as a mask.
Next, as shown in
FIGS. 21A
,
21
B and
21
C, the second insulating film
12
is etched using the gate masking pattern
31
as a mask.
Next, as shown in
FIGS. 22A
,
22
B and
22
C, the second floating gate electrode layer
13
b
and the first floating gate electrode layer
13
a
are etched using the gate masking pattern
31
as a mask. Thereby, the stacked gate structure is obtained in which the floating gate electrode
13
in the form of two layers and the control gate electrode
14
are stacked. In this stage, a two-layer gate structure which is the same as that shown in
FIG. 18A
is left below the word lines in the direction of gate width W in the memory cell area. Also, in this state, the top of the device isolation regions
30
is above the Si substrate surface level. That is, a step is formed between the top of the device isolation region
30
and the Si substrate surface.
After that, the stacked gates are covered with a capping material and then an interlayer insulating film is formed over the entire substrate of the substrate. Next, contact windows are formed in the interlayer insulating film and an interconnect layer is then formed.
In forming the interlayer insulating film, a BPSG film in which impurities, such as boron or phosphorus, are mixed into a silicon dioxide film to increase melting performance is deposited and then planarized by means of CMP. After that, contact windows are formed in the interlayer insulating film by dry etching. In this case, unless the etch selectivity between the capping material and the interlayer insulating film is high, the capping material on the gates will also be etched to reduce the thickness or removed thoroughly to expose the gates. Then, in filling the contact material into the contact windows, failures may occur in which the gates and the contact material are short-circuited. Thus, as the capping material use is made of a silicon nitride-based film which has relatively high etch selectivity to the silicon dioxide-based interlayer insulating film.
In the structure of
FIGS. 22A-22C
realized by the gate preformation process, the device isolation insulating film
30
is formed to self-align to the sidewall of the floating gate electrodes
13
a
and its top is above the Si substrate surface level. That is, the active regions in the Si substrate are surrounded by the device isolation insulating film
30
whose top is above the surface level of the active regions.
However, it has become clear that such a structure as described above causes various problems as device dimensions are scaled down.
In many cases, as a contact window etching stopper a silicon nitride film is deposited on the substrate surface so as to prevent contact windows from being formed too deep in those portions of the interla
Matsui Michiharu
Mori Seiichi
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