Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-27
2003-08-05
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S379000, C257S380000, C257S382000, C257S384000, C257S536000
Reexamination Certificate
active
06603172
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having such elements as a capacitor, a resistor, and a transistor mounted thereon, of which high integration and low cost are required.
A manufacturing process for a conventional semiconductor device having a MOS transistor, a capacitor, and a resistor mounted thereon (combined analog and digital circuit) has been implemented by a normal manufacturing process for the MOS transistor (process for digital devices) combined with an additional manufacturing process for the capacitor and resistor (process for analog devices).
In a MOS transistor formed recently by the normal manufacturing process for digital devices, it has become necessary to reduce the resistance of the gate electrode and source/drain diffusion layers by forming a polycide gate or salicide or selectively growing a metal material, thereby increasing the operating speed of the transistor and reducing the area occupied thereby.
On the other hand, a resistor formed by the process for analog devices should be composed of a high-resistance material to occupy a reduced area as well as have accurately controlled resistance. The resistor is normally formed by using a diffusion layer formed simultaneously with the source/drain regions of the MOS transistor, a polysilicon layer which is to form the gate of the MOS transistor, or either one layer of a two-layer polysilicon electrode forming a capacitor. However, since the demand for a higher-speed, smaller-area MOS transistor has reduced the resistance of the gate electrode and source/drain diffusion layers as described above, the area occupied by the resistor will be increased if the desired resistance is imparted thereto, which leads to the problem that the area occupied by the whole semiconductor device cannot be reduced.
To prevent the problem, there has conventionally been proposed such a method as disclosed in U.S. Pat. No. 4,949,153, wherein an insulating film is formed on a region intended to have relatively high resistance prior to silicidization in a salicide process, which allows a layer with relatively high resistance to be formed simultaneously with the formation of a low-resistance layer. The process of manufacturing an N-channel MOS transistor and a resistor discussed in the foregoing publication will be described with reference to FIGS.
10
(
a
) to
10
(
g
).
First, in the step shown in FIG.
10
(
a
), an isolation
22
is formed by a process of, i.e., trench isolation in a P-well
21
formed in a silicon substrate. Subsequently, a first insulating film
23
composed of a silicon oxide film is formed by, e.g., pyrogenic oxidation, followed by a polysilicon film deposited by, e.g., CVD to serve as a resistor. Thereafter, arsenic ions are implanted in the polysilicon film, which is subjected to a thermal treatment for activation. Thereafter, a desired resist film (not shown) is formed and used as a mask in dry etching for patterning the polysilicon film into a first conductor film
24
.
Next, as shown in FIG.
10
(
b
), the first insulating film
23
is removed by wet etching and a gate oxide film
25
a
is formed. During the formation step, a second insulating film
25
b
composed of an oxide film is also formed on the top and side surfaces of the first conductor film
24
. However, since polysilicon is more likely to be oxidized than single-crystal silicon, the second insulating film
25
b
is thicker than the gate oxide film
25
a
. Thereafter, a second conductor film
26
composed of a polysilicon film is deposited by, e.g., CVD to form a gate electrode. After that, arsenic ions are implanted in the second conductor film
26
.
Next, as shown in FIG.
10
(
c
), the second conductor film
26
is patterned by dry etching using the desired first resist film
27
as a mask to form a gate electrode
26
a.
Next, as shown in FIG.
10
(
d
), impurity ions are implanted in the P-well
21
to form N-type low-concentration diffusion layers
29
, which are to serve as N-type LDD (Lightly Doped Drain) layers, followed by a silicon oxide film
28
deposited by, e.g., CVD to serve as a sidewall insulating film. The silicon dioxide film
28
forms sidewalls for the MOS transistor as well as a protective film from silicidization in the subsequent step. At this stage, a second resist film
35
is formed on the silicon oxide film
28
to correspond to the region with high resistance of the first conductor film
24
composing the main portion of a resistor.
Next, as shown in FIG.
10
(
e
), anisotropic etching is performed by using the second resist film
35
as a mask to remove the silicon oxide film
28
, which is partially left on the side surfaces of the gate electrode
26
a
of the MOS transistor and on the side surfaces of the first conductor film
24
that is to serve as the resistor, to form sidewall insulating films
28
a
. The silicon oxide film
28
is also left on the region previously covered by the resist film
35
as the mask to form an on-resistor insulating film
28
b
. Impurity ions are further implanted in the P-well
21
to form N-type high-concentration diffusion layers
30
, which are to serve as the source/drain regions, and subjected to a thermal treatment for activation.
Next, as shown in FIG.
10
(
f
), a high-melting-point metal such as titanium is deposited and subjected to a rapid-heating thermal treatment so that silicide films
31
composed of a reaction product of silicon and titanium are formed on regions uncovered with the silicon oxide film and composed of silicon, in which the surfaces of the gate electrode
26
a
, N-type high-concentration layers
30
, and first conductor film
24
are exposed. After that, the unreacted portions of the titanium film unformed with the silicide films
31
are removed by wet etching.
Next, as shown in FIG.
10
(
g
), an interlayer insulating film
32
, CW contacts
33
, metal interconnect layers
34
are formed sequentially on the substrate, resulting in the semiconductor device on which the N-channel MOS transistor having the low-resistance gate, source, and drain and the resistor composed of the high-resistance region are mounted.
Although the foregoing embodiment has used the two-layer polysilicon film consisting of the first and second conductor films
24
and
26
, it is also possible to use the second conductor film
26
, which is to form the gate of the MOS transistor, to compose the first conductor film
24
that is to serve as the resistor. However, since trends have required higher capacitance from a capacitor used in an analog circuit, it is preferred in the future to use a capacitor having a two-layer conductor film such that an insulating film between the two layers is used as a capacitor (2PS capacitor).
Next, a description will be given to a prior art related to the plan configuration of the resistor.
As shown in FIG.
11
(
a
), the resistor typically has a meander plan configuration composed of a conductor film bent back several times. Specifically, linear portions
36
b
and fringe portions
36
c
corresponding to the bent portions alternate between contact formation regions
36
a
at both ends. However, the presence of the fringe portions
36
c
, which is varied in configuration, causes variations in resistance and in spreading resistance. As a result, the accuracy of the resistor is lowered even when a specified resistance value is intended for the resistor.
To eliminate the problem, there may be cases where the following method is implemented. As shown in FIG.
11
(
b
), the resistor
36
is composed of the plurality of discrete linear portions
36
b
parallel with each other. Both ends of the linear portions
36
b
are formed with the respective CW contacts
33
to be connected to the upper metal interconnect layers
34
. Each adjacent two of the linear portions have their ends connected to each other via the two CW contact layers
33
and the metal interconnect layers
34
so as to constitute the whole single resistor. The resistor thus constituted is for preventing variations in resistance, since no bent
Matsuzawa Akira
Segawa Mizuki
Yabu Toshiki
Fenty Jesse A.
Lee Eddie
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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