Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2000-11-01
2003-08-19
Cuneo, Kamand (Department: 2827)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S458000, C438S113000, C438S115000, C438S114000, C438S464000, C257S620000, C257S622000, C257S623000, C257S618000
Reexamination Certificate
active
06607970
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-321416, filed Nov. 11, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device that is sealed in resin in the form of a silicon wafer and a method of manufacturing the same.
A method of manufacturing semiconductor devices called CSPs (Chip Size Packages) will be described with reference to
FIG. 17
to FIG.
20
. First, as shown in
FIG. 17
, connection pads
2
are formed on the upper surface of a silicon wafer (semiconductor wafer)
1
. An insulating film
3
is then formed, covering the upper surface of the wafer
1
and the connection pads
2
, except the center part of each connection pad
2
. Wirings
5
are formed, each on a limited region of the insulating film
3
and on the center part of the connection pad
2
, which is exposed through an opening
4
made in the insulating film
3
. Pillar-shaped electrodes or column electrodes
6
are formed, each on one end of the wiring
5
. Regions
7
shown in
FIG. 17
correspond to dicing streets.
Next, as shown in
FIG. 18
, a seal film
8
made of epoxy-based resin or the like is formed on the upper surface of the resultant structure including the pillar-shaped electrodes
6
. The seal film
8
is a little thicker than the pillar-shaped electrodes
6
are tall. The seal film
8
therefore covers the pillar-shaped electrodes
6
. Then, the seal film
8
is polished at its upper surface until the tops of the pillar-shaped electrodes
6
are exposed as is shown in FIG.
19
. Further, the silicon wafer
1
is cut along the dicing streets
7
. Chips, or semiconductor devices
9
, are thereby manufactured as is illustrated in FIG.
20
.
The semiconductor devices
9
have been made by cutting the silicon wafer
1
that has the seal film
8
formed on it along the dicing streets
7
. The four sides of each semiconductor device
9
are therefore exposed. At the exposed sides, water or moisture may enter the interface between the insulating film
3
(protective film) and the seal film
8
, and may oxidize the wirings
5
and the like. Moreover, a crack or cracks may develop in the interface between the insulation film
3
and the seal film
8
.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that is resin-sealed at the sides, too, which are exposed when the device is cut from a wafer.
According to an aspect of the invention there is provided a semiconductor device which comprises a semiconductor substrate and a seal film. The substrate has an upper surface, a lower surface opposing the upper surface, sides extending between the upper and lower surfaces, and a plurality of outer connection terminals formed on the upper surface. The seal film covers the upper surface of the semiconductor substrate, exposes each of the outer connection terminals at one surface, and covers the sides to at least half the thickness of the semiconductor substrate.
According to another aspect of invention there is provided a method of manufacturing a semiconductor device. The method comprises the steps of: preparing a semiconductor wafer having an upper surface, a lower surface opposing the upper surface, sides extending between the upper and lower surfaces, and a plurality of outer connection terminals formed on the upper surface; making trenches in those parts of the semiconductor wafer which lie between chip-forming regions thereof, each trench reaching at least half the thickness of the semiconductor wafer, and forming a seal film on the upper surface of the semiconductor wafer, filling the trenches and exposing the outer connection terminals at one surface; and cutting the seal film along the trenches, removing those parts of the seal film which have a smaller width than the trenches.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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Masatoshi Yasunaga et al: “Chip Scale Package* (CSP) A Lightly Dressed LSI Chip”, Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology Symposium, New York, U.S., IEEE vol. Symp. 16, pp. 169-176 XP000530088, ISBN: 0-7803-2038-7, p. 169-p. 171; Figures 1-6.
Casio Computer Co. Ltd.
Cuneo Kamand
Frishauf Holtz Goodman & Chick P.C.
Thai Luan
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