Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2002-02-06
2003-04-01
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S258000
Reexamination Certificate
active
06541357
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-370313, filed on Dec. 4, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a DRAM embedded with a logic circuit and a DRAM and a manufacturing method thereof.
It has been demanded to speed-up of operation of a system LSI. Responding to this demand, a plurality of types of devices having functions different from each other are mounted on a single semiconductor substrate. One example thereof is the system LSI including a logic circuit for controlling the DRAM, wherein the logic circuit and the DRAM are embedded into one single chip. Thus, the system LSI embedded with the logic circuit and the DRAM is referred to as an embedded DRAM (which will hereinafter simply abbreviated to eDRAM).
The eDRAM is constructed of a memory region where a memory array of the DRAM is provided, and a logic region to provide the logic circuit for controlling an operation of the memory and performing arithmetic operations.
A field effect transistor (FET)used for the memory device (which will hereinafter be called the memory device FET) is different in terms of its function from an FET used for the logic device (which will hereinafter be called the logic device FET). Accordingly, these two types of FETs are structured differently. Generally, separate manufacturing processes are required for providing the plurality of device FETs having the structures different from each other on the single semiconductor substrate.
On the other hand, if scheming to simplify the manufacturing processes by making common the processes for manufacturing the plurality of device FETs having the structures different from each other, it is difficult to obtain functions and performances demanded of the respective FETs.
It is therefore difficult to obtain a reliability of a gate insulating layer of the memory device FET, attain a speed-up of the logic device FET and reduce a manufacturing cycle time at the same time. Namely, there is a trade-off relationship between the enhancement of the function and performance of the eDRAM and the reduction and simplification of the manufacturing processes.
Thus, conventionally, there must be a compromise either on the side of enhancing the function and performance of the system LSI or on the side of reducing and simplifying the manufacturing processes.
The speed-up of the logic device FET of the eDRAM has been attained over the recent years by making its size hyperfine and decreasing a thickness of the gate insulating layer. The decrease in the thickness of the gate insulating layer leads to an increase in electric field applied to the gate electrode. A depletion layer is thereby formed in the gate electrode. This depletion layer exerts substantially the same influence as increasing the thickness of the gate insulating layer upon the logic device FET. Namely, a capacitance C
OX
between the gate electrode and the semiconductor substrate decreases. With the decrease in the capacitance C
OX
, a threshold value of the logic device FET substantially rises, while an electric current flowing to the logic device FET decreases. Namely, a current drive capability of the logic device FET declines.
Particularly, the P-type FET receives a larger influence of the depletion layer in the gate electrode than the N-type FET. It is because boron in the P-type gate electrode is harder to activate than phosphorus or arsenic in the N-type gate electrode.
Such being the case, polycrystalline silicon germanium (which will hereinafter be abbreviated to poly-SiGe) replacing polycrystalline silicon is used as the gate electrode in order to further activate boron in the P-type FET.
The manufacturing processes of such system LSI can be reduced by using poly-SiGe also for the gate electrode of the memory device FET in the memory array. Germanium contained in poly-SiGe, however, diffuses over the gate insulating layer, thereby exerting an adverse influence upon a quality of the gate insulating layer, e.g., an interface trap density and a fixed charge density. If the quality of the gate insulating layer is deteriorated, there decreases the time for the memory device FET to retain the electric charges. Namely, there arises a problem in which a memory device FET's capability of retaining the electric charges declines because of using poly-SiGe for the gate electrode.
Further, in the eDRAM, silicide is provided in self-alignment manner on upper portions of the gate electrodes of the logic device FET and of the memory device FET, respectively, employing a so-called SALICIDE (Self-ALIgned siliCIDE) process. Silicide is used also for a word line. Silicide serves to decrease both of a resistance of the gate electrode and a resistance of the word line connected to the memory device FET. A speed of the eDRAM is thereby increased.
If a thickness of the poly-SiGe layer is comparatively small, a metal in silicide diffuses up to the gate insulating layer. Accordingly, the poly-SiGe layer must be thick enough for the metal within the silicide not to reach the gate insulating layer.
On the other hand, in the logic device FET, a short channel effect such as punch-through and so on is caused due to a hyperfine structure. The impurities are implanted at an angle of inclination from a direction perpendicular to the surface of the semiconductor substrate for preventing the short channel effect. This impurity implantation is known as a halo implantation.
A distance between the adjacent gate electrodes in the logic region and a distance between the adjacent gate electrodes in the memory region, are designed the same in some cases. Namely, there exist some semiconductor devices in which the distance between the adjacent gate electrodes in the logic region is determined based on a minimum design rule.
In such a case, if a height of the gate electrode from the surface of the semiconductor substrate is comparatively large, the halo implantation is hindered by the adjacent gate electrode in the logic region, and the impurities are not implanted into the semiconductor substrate in some cases. Accordingly, the height of the gate electrode in the logic region must be low to such an extent that the impurities can be implanted by the halo implantation.
Hence, the poly-SiGe layer must be thick enough for the metal in silicide not to reach the gate insulating layer and be thin enough to enable the halo implantation to be carried out.
Moreover, a higher voltage is applied to the gate insulating layer in the memory device FET than in the logic device FET. Hence, a withstand voltage of the memory gate insulating layer of the memory device FET must be higher than that of the logic gate insulating layer of the logic device FET. If the gate insulating layer of the memory device FET is too thin, the electric charges conduct by direct tunneling) the gate insulating layer, and consequently the electric charge retention capability declines. This leads to deterioration of a retention time of the memory device FET.
Accordingly, the memory gate insulating layer must be formed thicker than the logic gate insulating layer.
It is, however, impossible to provide the gate insulating layers each having a different thickness on the same semiconductor substrate in the same process. Therefore, the gate insulating layers are provided in different processes respectively in the memory region and in the logic region.
A conventional method for providing the gate insulating layers each having the different thickness on the same semiconductor substrate, involves at first providing a comparatively thick memory gate insulating layer, e.g., a silicon oxide layer over the entire semiconductor substrate, providing next a mask layer on the gate insulating layer in the memory region, and selectively removing the gate insulating layer ex
Dang Phuc T.
Kabushiki Kaisha Toshiba
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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