Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-10
2003-09-02
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S342000, C257S343000, C257S344000, C257S409000
Reexamination Certificate
active
06614075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to LD (Lateral Double Diffused) MOS transistor technology which is used for a high voltage element for e.g. liquid crystal driving IC.
2. Description of the Related Art
Now, an LDMOS transistor structure refers to a structure in which impurities with a different conduction type are diffused in a diffused region formed on surface of a semiconductor substrate to form another diffused region and a difference in the horizontal diffusion between these diffused regions is employed as an effective channel length. This structure, in which a short channel is formed, can constitute an element with low “on” resistance.
FIGS. 11A and 11B
are a sectional view for explaining a conventional LDMOS transistor. A N-channel LDMOS transistor structure is illustrated. Although the structure of a P-channel LDMOS transistor structure is not explained here, it is well known that the same structure can be adopted except for its conduction type.
In
FIG. 11A
, reference numeral
1
denotes a semiconductor substrate with a first conduction type, e.g. P-type, and reference numeral
2
denotes a P-type well region. A P-type body region
3
is formed within the P-type well region
1
. An N-type diffused region
4
is formed within the P-type body region
3
. Another N-type diffused region
5
is formed apart from the N-type diffused region
4
. A gate electrode
7
is formed on the surface of the substrate
1
through a gate insulating film
6
. A channel region
8
is formed in the surface region of the P-type body region
3
immediately below the gate electrode.
The N-type diffused region
4
is used as a source region whereas the N-type diffused region is used as a drain region. The N-type well region
2
below a LOCOS oxide film
9
is used as a drift region. Further, reference numerals
10
and
11
denote a source electrode and drain electrode, respectively. Reference numeral
12
denotes a P-type diffused region for assuming the potential of the P-type body region
3
and reference numeral
13
denotes an interlayer insulating film.
In the above LDMOS transistor, since the N-type well region
2
is formed by diffusion, a high impurity concentration is given on the surface of the N-type well region, a current is apt to flow in the surface of the N-type well region, thereby realizing a high withstand voltage. The LDMOS transistor having such a configuration is referred to as a surface relax type (RESURF)LDMOS. The dopant concentration of the drift region in the N-type well region
2
is set so as to satisfy the condition of RESURF. Such a technique is disclosed in JP-A-9-139438.
However, since the impurity concentration is high in the surface of the N-type well region, P-type impurity for forming the P-type body region
3
cannot diffuse sufficiently. Therefore, as shown in
FIG. 11B
, the edge of the P-type body region
3
approaches the source region (N-type diffused region
4
) so that the channel region
8
may be not be formed to have a suitable size (see indicated arrow A).
SUMMARY OF THE INVENTION
An object of the invention is to provide a method of manufacturing a semiconductor device which can satisfy the requirements of a high withstand voltage and reduced “on” resistance.
In order to solve the above problem, for example as shown in
FIG. 1
, a first conduction type body region (e.g. P-type body region
3
) is formed by ion-implanting first conduction type impurities (e.g. boron ions) using as a mask a gate electrode patterned so that its side wall is tapered to be more narrow toward the top. Further, a second conduction type source region (e.g. N-type diffused region) is formed by ion-implanting second conduction type impurities (e.g. phosphorus ions) using as a mask the gate electrode
7
A. In this way, by using the tapered shape of the gate electrode
7
A as a mask during the ion-implantation and controlling a depth of the implantation, relative positions can be optimized among the P-type body region
3
, source region and channel region
8
.
In accordance with the invention, in an LDMOS transistor in which two kinds of impurities with different conduction types are diffused using a gate electrode as a mask and a difference in the horizontal diffusion between diffused regions is employed as an effective channel length, the gate electrode is patterned so that its side wall is tapered to be more narrow toward the top. In this configuration, it is possible to the problem that the impurities with an opposite conduction type adjacent to the drift region cannot diffuse sufficiently owing to the surface concentration of the drift region so that the channel region cannot be formed properly.
In accordance with the invention, the drift region is formed using a difference in the diffusion length is used between at least two kinds of second conduction type impurities with different diffusion coefficients and at least one kind of first conduction type impurities having a diffusion coefficient approximately equal to or larger than at least one kind of the second conduction impurities. This simplifies a process of manufacturing the semiconductor device.
Further, in accordance with the invention, since the gate electrode is structured so that its side wall is tapered to be more narrow toward the top, it is possible to overcome the danger that when the conductive film formed on the entire substrate surface inclusive of the gate electrode for the gate electrode of the other transistor to be formed on the same substrate is patterned for removal, the conductive film is left on the side wall of the gate electrode, thereby giving rise to poor short-circuiting.
REFERENCES:
patent: 3953255 (1976-04-01), Combs, Jr.
patent: 4823173 (1989-04-01), Beasom
patent: 5177571 (1993-01-01), Satoh et al.
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5872382 (1999-02-01), Schwalke et al.
Akaishi Yumiko
Kikuchi Shuichi
Mori Shinya
Suzuki Takuya
Tsukada Yuji
Fish & Richardson P.C.
Mondt Johannes P
Sanyo Electric Co,. Ltd.
Tran Minh Loan
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