Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-18
2003-04-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S275000
Reexamination Certificate
active
06555868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and particularly relates to a semiconductor device which is improved for increasing performance and reliability. The invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In recent years, a flash memory which is a kind of nonvolatile semiconductor memory device has been expected as a useful memory device for the next generation because it can be manufactured at a lower cost than a Dynamic Random Access Memory (DRAM), and therefore.
FIG. 59
is a cross section of a memory cell portion of a flash memory in the prior art.
The structure in
FIG. 59
is provided at a surface of a semiconductor substrate
1
with a source region
2
connected to a source line and a drain region
3
connected to a corresponding bit line. A floating gate electrode
5
is arranged on semiconductor substrate
1
with a tunnel oxide film
4
therebetween. A control gate electrode
7
which is connected to a corresponding word line is arranged on floating gate electrode
5
, and a control gate and floating gate interlayer insulating film
6
, which is generally formed of an oxide film, a nitride film and an oxide film (ONO film), is interposed between control gate electrode
7
and floating gate electrode
5
.
An FN (Fowler-Nordheim) current phenomenon, a Channel Hot Electron (CHE) phenomenon or the like is caused in tunnel oxide film
4
, which is located immediately under floating gate electrode
5
, for injecting electrons into floating gate electrode
5
or removing electrons therefrom so that erasing or writing is performed. Depending on the state of electrons in floating gate electrode
5
, the binary state of the threshold is determined, and the “0” or “1” is read out depending on this state.
In the nonvolatile semiconductor memories of the floating gate type such as a flash memory described above and an EEPROM, NOR-type array structures are used most generally. In the NOR-type array, contacts are formed in a drain diffusion layer of memory cells in each row, and bit lines formed of metal interconnections or polycide interconnections are arranged in the row direction. Thus, the NOR-type array structure has the gate interconnections of the memory cells in the respective columns and the bit line are, which are arranged in a matrix form.
FIG. 60
is a circuit diagram showing the NOR-type array.
FIG. 61
shows a layout of the NOR-type array.
FIG. 62
is a cross section taken along line A—A in FIG.
61
.
FIGS. 62 and 63
are cross sections taken along lines B—B and C—C in
FIG. 61
, respectively. In these figures, “
8
” indicates a bit line contact, “
9
” indicates an active region, “
10
” indicates an isolating oxide film, and “
11
” indicates an oxide film.
Referring to these figures, all source regions
2
of memory cells in each block, which is formed of memory cells of, e.g., 512 Kbits, are connected. For connecting all source regions
2
in this manner, a self-align source structure may be used very effectively for miniaturizing the memory cells.
For connection of source region
2
of each memory cell, the self-align source structure does not employ such a manner that a contact is extended to a diffusion layer of each memory cell, and the contacts thus formed are connected by metal interconnections. In the self-align source structure, as shown in
FIG. 65
, control gate electrodes
7
of the memory cells are first formed, and resists
12
having openings which expose only source regions
2
are formed. Ends of resists are located on control gate electrodes
7
. Referring to
FIGS. 65 and 64
, etching is effected on a structure masked with resists
12
and control gate electrodes
7
so that an isolating oxide film which is present in source regions
2
is removed. Further, ion implantation of arsenic or the like is effected on source regions
2
. Thereby, source regions
2
are connected together in the column direction by the diffusion layer. These are formed in a self-aligned fashion. In
FIG. 64
, dotted lines represent portions of the isolating oxide film which are removed by the etching.
All the source regions of the memory cells may be formed of the active regions, and may be connected by metal interconnections. This structure requires an alignment margin so that a gate distance in the source region must be large. In the self-align source technique, however, all the source regions of the memory cells are formed of the active regions, and are connected by the diffusion layers so that the distance between the gates located on the opposite sides of the source region in the memory cell can be determined in accordance with the minimum design rule. Thus, the miniaturization of the memory cells can be achieved.
In accordance with remarkable reduction in design rule in recent years, however, it is required in the flash memory employing the self-align source structure to reduce further the distance between the gates on the opposite sides of the source region of the memory cell, which can be formed in accordance with the minimum design rules.
For performing the write and erase operations in the flash memory, an FN tunnel current or a CHE tunnel current must be produced on the control gate electrode, source/drain and substrate. For this, a high voltage of 10 V or more is required. For handling such a high voltage, a peripheral transistor must have a higher breakdown voltage than a peripheral transistor used in a DRAM or an SRAM.
A high breakdown voltage of the transistor can be effectively achieved by optimizing a source/drain structure and employing a thick sidewall spacer.
Referring to
FIG. 66
, if a thick sidewall is used in a flash memory device having a miniaturized structure for achieving a peripheral circuit having a high breakdown voltage, the sidewall spacer fills a narrow space located on source region
2
and formed between neighboring gates in the memory cell. In this case, a stress is caused and applied to the substrate due to expansion and contraction of the sidewall insulating film filling the narrow space on source region
2
during later processing of oxidation and high-temperature annealing. As a result, crystal defects
13
occur in substrate
1
. Consequently, leakage occurs between the source and drain of the memory cell, resulting in remarkable reduction in device performance. If crystal defects
13
extend to a position under tunnel oxide film
4
, reliability such as endurance and retention remarkably lower.
FIG. 67
shows a flow from formation of the layered gate to formation of the sidewall spacer in a first prior art.
Referring to
FIG. 68
, first and second layered gates
20
a
and
20
b
are formed. Referring to
FIG. 69
, a resist pattern
28
having an opening exposing only the source portion of the cell is formed by photolithography. Using resist pattern
28
as a mask, etching is effected to remove the isolating oxide film, and ion implantation is performed for providing the diffusion layer interconnection in the etched portion. Thereby, the self-align sources is completed. Referring to
FIG. 70
, resist pattern
28
is removed. Referring to
FIG. 71
, an insulating film
14
for forming a sidewall spacer, which will be referred to as a “sidewall insulating film” hereinafter, is deposited. Referring to
FIG. 72
, sidewalls of floating gates
5
and control gates
7
are oxidized for the purpose of rounding the ends on both the source and drain sides of floating gates
5
. Referring to
FIG. 73
, etch-back is effected on sidewall insulating film
14
.
In the prior art shown in
FIG. 72
, sidewall insulating film
14
, which is located on source region
2
and between the gates, expands and contracts to apply a stress to the substrate portion located under source region
2
when thermal processing for a high-temperature oxidization of the sidewall is performed in an oxygen atmosphere at 800-900° C. This stress causes crystal defects
13
shown in FIG.
66
.
FIG. 74
is a flow showing a
Onakado Takahiro
Shimizu Satoshi
Hoang Quoc
McDemott, Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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