Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-07
2003-05-06
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S392000, C257S393000, C257S401000, C438S151000, C438S221000, C438S225000, C438S689000, C438S644000
Reexamination Certificate
active
06559489
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically to a semiconductor device having a contact hole and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In recent years, as the semiconductor devices has undergone further miniaturization, the distance between the electrodes formed on a surface of a semiconductor substrate has become smaller. In addition, between those electrodes, the amount of margin in the distance between an electrode and a contact hole formed in an interlayer insulating film is also becoming smaller.
Accordingly, technologies relating to the so-called self-aligned contact hole is being developed in which an etching stopper such as a nitride film is formed to cover a gate electrode, and in which a contact hole is not allowed to reach the gate electrode even when the contact hole and the gate electrode overlap in a planar manner. For instance, a semiconductor device having a contact hole formed in a self-aligned manner is described in Japanese Patent Laying-Open No. 9-134956.
FIG. 23
is a cross sectional view of a conventional semiconductor device described in the above publication. As seen in
FIG. 23
, an element isolating region
514
is formed on a surface of a semiconductor substrate
513
. In addition, a conductive region
513
a
is formed in the part of the surface of semiconductor substrate
513
where element isolating region
514
is not formed.
An interconnection
516
is formed on semiconductor substrate
513
with a gate insulating film
515
interposed therebetween. A silicon oxide film
517
is formed on interconnection
516
, and sidewalls
518
are formed in contact with interconnection
516
.
Further, an oxide film
519
and an etching stopper film
520
are formed covering element isolation region
514
, sidewalls
518
, and silicon oxide film
517
. Etching stopper film
520
consists of an insulating film containing nitrogen molecules such as a silicon nitride film.
An interlayer insulating film
521
is formed covering etching stopper film
520
. In interlayer insulating film
521
, a hole reaching conductive region
513
a
is formed. A contact
522
is formed within the hole. An upper-layer interconnection
523
is formed in contact with contact
522
.
When manufacturing such a semiconductor device, oxide film
519
and etching stopper film
520
are formed to cover interconnection
516
, silicon oxide film
517
, and sidewalls
518
. Interlayer insulating film
521
is formed to cover etching stopper film
520
, and then a hole reaching conductive region
513
a
is formed in interlayer insulating film
521
. At this time, interlayer insulating film
521
is etched with the condition that the etching rate of interlayer insulating film
521
is greater than the etching rate of etching stopper film
520
. Therefore, a portion of etching stopper film
520
where it is thick in the vertical direction, i.e. the portion of etching stopper film
520
having a large thickness in the vertical direction where etching stopper film
520
is formed along sidewalls
518
, is not etched easily. As a result, the etching of sidewalls
518
can be prevented so that the hole will only reach conductive region
513
a
even when a large hole is formed, and is less likely to reach sidewalls
518
and interconnection
516
.
Thus, a hole can be formed without allowing the hole to reach interconnection
516
even when the margin of the distance between the hole and interconnection
516
is small.
The problems that arise in a conventional semiconductor device as shown in
FIG. 23
will be described below.
Recently, researches are made in relation not only to the miniaturization but also to a higher-speed operation of a semiconductor device. In order to increase the operating speed of a semiconductor device, there is a need to reduce the contact resistances between various conductive layers formed in a semiconductor device. Further, the electric resistance of a conductive layer itself needs to be reduced.
A problem involved in a conventional semiconductor device as shown in
FIG. 23
is that the contact resistance between contact
522
and conductive region
513
a
is too high to achieve a high-speed operation of the semiconductor device.
Moreover, the cross section of upper-layer interconnection
523
must be made larger in order to reduce the electric resistance of upper-layer interconnection
523
. For this purpose, the width or the thickness of upper-layer interconnection
523
might be increased. If the width of upper-layer interconnection
523
is increased, however, the semiconductor device cannot be miniaturized. Moreover, if the thickness of upper-layer interconnection
523
is increased, the evenness of the semiconductor device cannot be ensured. Therefore, conventionally, it was too difficult to enlarge the cross section of upper-layer interconnection
523
that a higher-speed operation of the semiconductor device could not be achieved.
SUMMARY OF THE INVENTION
Thus, the present invention is made to solve the above-described problems. An object of the present invention is to provide a semiconductor device capable of a high-speed operation and having a small contact resistance between two conductive regions as well as to provide a method of manufacturing such a semiconductor device.
Moreover, another object of the present invention is to provide a semiconductor device capable of a high-speed operation with a conductive layer having a small electric resistance as well as to provide a method of manufacturing such a semiconductor device.
A semiconductor device according to one aspect of the present invention is provided with a semiconductor substrate, a pair of low concentration impurity regions, a gate electrode, a protective film, an interlayer insulating film, a high concentration impurity region, and a conductive layer. Low concentration impurity regions having a relatively low impurity concentration are formed spaced apart from one another on a surface of the semiconductor substrate. The gate electrode is formed between the pair of low concentration impurity regions on the semiconductor substrate with a gate insulating film interposed between the gate electrode and the semiconductor substrate. The protective film covers the gate electrode. The interlayer insulating film covers the gate electrode and the protective film, and has a hole reaching an impurity region. The etching rate of the interlayer insulating film is greater than that of the protective film when a prescribed etchant is employed. The high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole, and has a relatively high impurity concentration within a low concentration impurity region. The conductive layer fills the hole such that it is electrically connected to the high concentration impurity region.
In a semiconductor device thus configured, the high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole so that the bottom of the hole forms the high concentration impurity region. Since the conductive layer is provided to fill the hole such that an electrical connection to the high concentration impurity region is established, the conductive layer is electrically connected to the impurity region that has a relatively high impurity concentration. Thus, the hole and the surface of the high concentration impurity region that is connected through the hole do not shift out of position. Therefore, an increase in the contact resistance between the conductive layer and the high concentration impurity region can be prevented, and a high-speed operation of the semiconductor device is achieved.
Preferably, the protective film includes a nitride film and the interlayer insulating film includes an oxide film.
Moreover, the protective film preferably is at least one of a silicon oxynitride film (SiON) and a s
Kosugi Ryuichi
Ohbayashi Shigeki
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3024372