Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-01-29
2003-07-22
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S690000, C257S696000, C257S734000, C257S737000
Reexamination Certificate
active
06597070
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device which has a structure to avoid damages or the like of metal bumps due to differential thermal expansion and a method of manufacturing the same.
2. Description of the Related Art
In recent semiconductor devices, high integration of semiconductor chips to be contained in these semiconductor devices have brought effects of miniaturizing and thinning the semiconductor devices themselves, and higher performance and higher operating speed of electronic equipment have been promoted. Further, in order to satisfy requirements of enhancing the performance, reducing the size and weight and increasing the operating speed in electronic equipment to be contained in semiconductor devices, new types of packages have been developed. For example, a package based on FCBGA (flip chip ball grid array) system in which highly densely packing can be performed has appeared in the market.
FIGS. 10A
to
10
D are side views showing a semiconductor device based on the FCBGA system.
FIG. 10A
shows a semiconductor chip, and
FIG. 10B
shows the mount state of the semiconductor chip. A semiconductor chip
40
has a plurality of electrode pads which are disposed in a predetermined arrangement on the peripheral portion thereof or on an active region, and metal bumps
41
are mounted on the respective electrode pads (FIG.
10
A). At the final user side, the semiconductor chip
40
is mounted on a multi-layered wiring board (mount board)
42
having electrodes which are arranged in the same pattern as the bump arrangement pattern (FIG.
10
B).
In general, when metal bumps
41
are formed of solder balls, the solder balls are reflowed under a predetermined temperature and fixed to the multi-layered board
42
. At this time, stress and strain occurs due to differential thermal expansion (the difference of coefficients of thermal expansion) between the semiconductor chip
40
and the multi-layered wiring board
42
, and thus the mount reliability is lost. In order to solve this problem, the following countermeasure is taken.
For example, aluminum nitride (AlN), mullite, ceramic materials such as glass ceramics, etc., which are expensive in price, may be used as materials of the multi-layered wiring board
42
. With these materials, the coefficient of linear expansion of the multi-layered wiring board
42
is approached to that of silicon which mainly constitutes the semiconductor chip
40
, whereby the mismatch of the coefficients of linear expansion is minimized to enhance the mounting reliability. This countermeasure is effective from the viewpoint of the enhancement of the mounting reliability. However, the materials of the multi-layered wiring board
42
are expensive in price, and thus the use thereof is limited to an expensive apparatus such as a super computer, a large-scale computer or the like.
In view of the foregoing situation, there has been developed such a technique that a multi-layered board using an organic material which is relatively low in price and has a large coefficient of linear expansion is used for device mounting, and an under fill resin is inserted between the multi-layered wiring board and a semiconductor chip to disperse shearing stress acting on bump connection portions, thereby reducing the stress and strain and enhancing the mounting reliability.
In the technique using the organic materials as described above, a cheap multi-layered wiring board can be used. However, when voids exist in the under fill resin or when the adhesion at the interface between the under fill resin and the semiconductor chip or the interface between the under fill resin and the multi-layered wiring board is degraded, an interface exfoliating phenomenon is induced in the reflow step, resulting in production of failed products.
The FCBGA type packages are generally used for large scale semiconductor integrated circuits (LSI) having high performance, however, the products are expensive. Therefore, when failed components other than semiconductor chips are detected in an electrically screening step after the semiconductor chips are mounted, the semiconductor chips are removed from the multi-layered wiring board and re-used. This semiconductor chip removing step needs a work of heating a good-quality semiconductor chip
40
which is sucked from the back side by a suction heating tool
43
as shown in
FIG. 10C
, pulling up the semiconductor chip
40
while melting the bump joint portions thereof and removing the semiconductor chip
40
from the multi-layered wiring board
42
.
At the time when the semiconductor chip
40
is removed, a metal bump
41
is damaged as shown in
FIG. 10D
, however, the chip body itself is not damaged. In the case of a semiconductor device designed so that the under fill resin is interposed between the semiconductor chip
40
and the multi-layered wiring board
42
, not only the metal bump
41
is damaged, but also the peripheral devices containing the multi-layered wiring board
42
and a passivation film for protecting the active region of the semiconductor chip are damaged. In this case, the recycling of the semiconductor chip
40
is substantially impossible. Therefore, even when a cheap multi-layered wiring board formed of organic material is used, the cost is not necessarily lowered.
SUMMARY OF THE INVENTION
The present invention has been implemented in view of the foregoing situation, and has an object to provide a semiconductor device and a method of manufacturing the same in which deforming stress acting on a metal bump is moderated with no under fill resin between a semiconductor chip and a multi-layered wiring board (mounting board) to thereby enhance the mounting reliability of the semiconductor chip, and also peripheral devices containing the mounting board, etc. are avoided from being damaged in a recycling step, thereby reducing the manufacturing cost.
In order to attain the above object, according to a first aspect of the present invention, a semiconductor device in which electrode pads formed on a semiconductor chip is connected to corresponding electrodes on a mounting board through metal bumps, is characterized by including: a passivation film which is formed in the semiconductor chip and has opening portions through which the electrode pads are exposed; first conductive members whose one end faces are connected to the electrode pads through the opening portions; second conductive members through which the other end faces of the first conductive members and the metal bumps are connected to one another; and an insulating resin layer having elasticity which covers the first conductive members, the second conductive members and the passivation film with the exception of the end faces of the second conductive members.
In the semiconductor device of the present invention, irrespective of no provision of under fill resin between the semiconductor chip and the mounting board, deforming stress acting on the metal bumps can be effectively absorbed/relaxed by the first conductive members and the second conductive members connected thereto both embedded in the elastic insulating resin layer, thereby enhancing the mounting reliability. Further, damages imposed on the peripheral devices containing the mounting board, etc. in the recycling step can be avoided, and semiconductor chips can be recycled when cheap mounting boards formed of organic materials are used, so that the manufacturing cost can be lowered.
Here, the metal bumps may be formed of solder added with metal materials containing Ag. With these materials, the coefficient of expansion of the metal bumps is adjusted to further improve the stress relaxation and thus further enhance the mounting reliability of the semiconductor device.
Further, it is preferable that each of the second conductive members is designed in a multi-stage structure having plural stages which are different in coefficient of thermal expansion from one anothe
Lebentritt Michael S.
NEC Electronics Corporation
Young & Thompson
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