Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2001-08-30
2002-12-31
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S488000, C438S778000, C438S771000, C438S772000
Reexamination Certificate
active
06500735
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-300442, filed on Sep. 29, 2000, the entire contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and also to a semiconductor device, in particular, a semiconductor device wherein an insulating film is directly formed on a layer of semiconductor device comprising polycrystalline silicon.
2. Description of the Related Art
A polycrystalline silicon layer which is directly deposited on a Si substrate by a CVD method, or which is formed through the heating of an amorphous layer or a polycrystalline layer that has been formed in advance is sometimes accompanied on the surface thereof with fine recessed/projected portions of the order of nanometers or more in roughness. When a conventional Si semiconductor element, in particular, an MOSFET transistor is manufactured by a polycrystalline silicon having such fine recessed/projected portions, the performance of the resultant element may sometimes deteriorated due to an influence from the configuration of interface, i.e. the aforementioned fine recessed/projected portions, between a layer of the polycrystalline silicon and an oxide film formed on the polycrystalline silicon layer. One of the main causes for this deterioration is a breakdown of insulating layer.
The MOSFET transistor is actuated by impressing an electric voltage between a metal electrode formed on an insulating layer and a polycrystalline silicon layer functioning as an active layer through the insulating layer. Therefore, if fine recessed/projected portions are existed at the interface between the polycrystalline silicon layer and the insulating film, a concentration of electric field is caused to locally generate at the interface, thus increasing the possibility of inviting the breakdown of insulating film, i.e. the breakdown of the element. Accordingly, if the breakdown of insulating film is to be avoided, the flattening of the interface between the polycrystalline silicon layer and the insulating film, in particular, projected portions of the polycrystalline silicon layer is indispensable.
Next, there will be explained about the surface features of the polycrystalline silicon layer in the case where an insulating film (oxide film) has been formed on the polycrystalline silicon layer by the conventional thermal oxidation.
FIG. 1
is a sectional TEM photograph illustrating the structure of an insulating film (oxide film) formed on the polycrystalline silicon layer by of the conventional thermal oxidation, and
FIG. 2
is a schematical diagram of the sectional TEM photograph of FIG.
1
.
Specifically, this structure was obtained by a process wherein a polycrystalline silicon layer
3
was deposited in advance via an insulating layer (oxide film layer)
2
on a Si substrate
1
, and then, a thermal oxide film (dry oxide film)
4
is formed at a temperature of 900° C. on the polycrystalline silicon layer
3
. As shown in
FIG. 2
, the curvature of the protruded tip end of polycrystalline silicon layer
3
was not substantially altered even after the oxidation thereof for forming the thermal oxide film
4
, i.e. the recessed/projected configuration of the interface between the oxide film and the polycrystalline silicon layer is retained substantially the same as that prior to oxidation of the polycrystalline silicon layer
3
. Namely, it is difficult, according to the conventional method of forming an oxide film by the thermal oxidation of polycrystalline silicon layer, to flatten the recessed/projected configuration of the interface between the oxide film and the polycrystalline silicon layer.
It is imperative, in order to further enhance the performance of semiconductor element, to minimize the recessed/projected configuration of the interface between the polycrystalline silicon layer and the oxide film formed thereon. As a countermeasure, the treatment of the polycrystalline silicon layer by CMP (Chemical Mechanical Polishing) or a solution of ammonium fluoride has been tried up to date. In the method using the CMP, though it is possible to physically flatten the surface of the polycrystalline silicon layer, it will lead to the introduction of crystal defects into the polycrystalline silicon layer during the CMP process, so that the influences on a resultant semiconductor element by the crystal defects would be unavoidable. In particular, if it is desired to realize the flattening of the order of several tens nanometers or less in surface roughness, since the magnitude of surface roughness is very small as compared with the inherent etching rate of the CMP, it is indispensable to optimize and closely control the conditions of the CMP. Therefore, the employment of the CMP for practical use is expected to be very difficult due to the problems such as high cost.
On the other hand, the treatment of the surface of polycrystalline silicon with a solution of ammonium fluoride is expected to invite an increased roughness of surface or an increase in magnitude of recess or projection due to the plane direction dependency of this etching solution. Further, even if the surface to be treated is formed of (111) plane, an inadvertent thinning of active layer will be unavoidably caused due to the etching by this etching solution. The polycrystalline silicon layer to be deposited on an insulating layer is frequently as thin as around sub-micrometers. If such a thin polycrystalline silicon layer is flattened, and then oxidized for forming an oxide layer, the thickness of the active layer may be decreased by a magnitude of the order of several tens nanometers due to the etching for this flattening by the etching solution and also due to this subsequent oxidation treatment. As a result, it may become difficult to secure a sufficient thickness of polycrystalline silicon which is required for the operation of semiconductor element. Additionally, since there is a possibility that the grain boundary of polycrystalline silicon may be selectively etched by the treatment using this etching solution, or that the polycrystalline silicon may be locally contaminated by the treatment using this etching solution, the employment of this ammonium fluoride solution for practical use is expected to be very difficult.
Moreover, the employment of the aforementioned CMP method or etching method inevitably invites an increase in number of manufacturing steps.
Namely, if the recessed/projected portion of the surface of polycrystalline silicon layer is to be reduced as minimum as possible by the aforementioned CMP method or etching method, additional steps may be required to be incorporated therein, thus necessitating an enormous time and labor for the development of the semiconductor element. As a matter of fact, if the aforementioned CMP method or etching method is to be employed for mass production, the reconsideration or replacement of manufacturing lines may be necessitated. Under the circumstances, it is now demanded to develop a technique for realizing a semiconductor element comprising a polycrystalline silicon layer having a minimal surface roughness, the technique being desirably featured in that it makes good use of the know-how of conventional manufacturing technique and manufacturing apparatus, that it is capable of achieving a high investment efficiency, and that it is possible to manufacture such a semiconductor element under an environment which is compatible with the conventional process of manufacturing a Si semiconductor device.
As explained above, in spite of the existing demand for the improvement in flatness of the interface between an insulating layer and a polycrystalline silicon layer of semiconductor element at the step of forming the insulating film on the polycrystalline silicon layer in the manufacture of a semiconductor device, no one has succeeded to provide a truly effective means up to date, so that th
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