Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2001-01-09

2002-08-13

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S306000

Reexamination Certificate

active

06433381

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same and, more particularly, to a semiconductor device having a COB type DRAM and to a method of manufacturing the same
2. Description of the Prior Art
In recent DRAM, the COB (Capacitor Over Bit-line) type in which an information storage capacitor is arranged on a bit line connected to a transistor is used, and a logic circuit is often also formed on the same substrate on which the transistor and capacitor are formed. A wiring structure in a memory cell region and a peripheral circuit region of the COB type DRAM is shown in a plan view of
FIG. 1
, for example.
In
FIG. 1
, a memory cell region
101
and a peripheral circuit region
102
are arranged on a semiconductor substrate
100
.
A plurality of active regions
103
are surrounded and partitioned by a device isolation insulating layer
104
in the memory cell region
101
of the semiconductor substrate
100
. A plurality of word lines that are also used as gate electrodes formed on the active regions
103
via a gate insulating film (not shown). Also, impurity diffusion layers
103
a
,
103
b
serving as source/drain are formed on both sides of the word line
105
in the active regions
103
. Accordingly, a plurality of MOS transistors are formed in the active regions
103
.
A plurality of bit lines
106
are formed on the word lines
105
via a first interlayer insulating film (not shown), and the bit lines
106
and the word lines
105
are extended to intersect orthogonally with each other.
The bit line
106
is connected to the active region
103
via a contact hole
107
formed in the first interlayer insulating film. The impurity diffusion layer
103
a
put between two word lines
105
is located at a position to which the bit line
106
is connected. Also, storage electrodes (not shown) of a capacitor
108
, that is formed on the bit line
106
via a second interlayer insulating film (not shown), are connected to the impurity diffusion layers
103
b
located near both ends of the active region
103
. The storage electrodes are connected to the impurity diffusion layers
103
b
via storage contact holes
109
formed in the first and second interlayer insulating films.
An active region
110
is surrounded and partitioned by the device isolation insulating film
104
in the peripheral circuit region
102
. A gate electrode
111
is formed on the active region
110
via a gate insulating film (not shown). Also, impurity diffusion layers
112
a
,
112
b
serving as source/drain are formed on both sides of the gate electrode
111
in the active region
110
of the semiconductor substrate
100
. Accordingly, a MOS transistor is formed in the active region
110
.
A first wiring
106
a
is formed integrally with the bit line
106
in the memory cell region
101
of the peripheral circuit region
102
. The first wiring
106
a
is connected to one impurity diffusion layer
112
a
in the active region
110
via a contact hole
128
b
. Also, a second wiring
113
is connected to the other impurity diffusion layer
112
b
via a contact hole
128
c.
In
FIG. 1
, a reference
114
denotes a lower wiring that has the almost same height as the gate electrode
111
in the peripheral circuit region
102
. A third wiring
115
formed in the same layer as the second wiring
113
is connected onto the lower wiring
114
.
Various structures of the bit lines
106
, the wirings
106
a
,
113
,
115
shown in
FIG. 1
are known. Then, these structures will be explained hereunder.
FIG. 2
is sectional view showing a semiconductor device having the DRAM and the peripheral circuit. The same references as those in
FIG. 1
denote the same elements.
FIG. 2
shows a sectional shape taken along a I—I line in
FIG. 1 and a
sectional shape taken along a II—II line.
In
FIG. 2
, a plurality of active regions
103
are surrounded and partitioned by the device isolation insulating layer
104
in the memory cell region
101
of the semiconductor substrate
100
. A plurality of MOS transistors are formed in these active regions
103
.
Upper and side surfaces of a plurality of word lines (gate electrodes)
105
, that are formed on the active regions
103
via the gate insulating film
105
a
, are covered with insulating films
121
,
122
. Also, impurity diffusion layers
103
a
,
103
b
serving as source/drain are formed on both sides of the word lines
105
in the active regions
103
.
Also, the active region
110
is formed in the peripheral circuit region
102
to be surrounded by the device isolation insulating layer
104
. A MOS transistor is formed in the active region
110
. More particularly, the gate electrode
111
is formed in the active region
110
of the semiconductor substrate
100
via the gate insulating film
111
a
, and the impurity diffusion layers
112
a
,
112
b
serving as source/drain are formed on both sides of the gate electrode
111
. Insulating films
121
,
122
are formed on an upper surface and side surfaces of the gate electrode
111
. In addition, a lower wiring
114
is formed on the device isolation insulating layer
104
in the peripheral circuit region
102
.
A first interlayer insulating film
123
is formed on the semiconductor substrate
100
to cover the MOS transistor. Also, contact holes are formed in the first interlayer insulating film
123
on the impurity diffusion layers
103
a
,
103
b
in the memory cell region
101
respectively. First and second contact plugs
125
a
,
125
b
are formed in these contact holes. The first contact plug
125
a
is connected to the impurity diffusion layer
103
a
formed between the word lines
105
, and the second contact plugs
125
b
are connected to the impurity diffusion layers
103
b
near both ends of the active regions
103
.
A second interlayer insulating film
126
is formed on the first interlayer insulating film
123
. A plurality of wiring trenches (recesses)
127
a
,
127
b
,
127
c
and a plurality of contact holes
128
a
,
128
b
,
128
c
,
128
d
are formed in the first interlayer insulating film
123
and the second interlayer insulating film
126
by the dual damascene method.
The wiring trenches
127
a
,
127
b
,
127
c
formed in the second interlayer insulating film
126
have a shape of the bit line
106
in the memory cell region
101
and shapes of the wirings
106
a
,
113
,
115
in the peripheral circuit region
102
respectively.
The contact hole
128
a
located in the memory cell region
101
is formed to reach the first contact plug
125
a
from a bottom of the wiring trench
127
a
. The contact holes
128
b
,
128
c
,
128
d
are formed to reach the impurity diffusion layers
112
a
,
112
b
and the lower wiring
114
from bottoms of the wiring trenches
127
a
,
127
b
,
127
c
respectively.
A barrier metal layer and a tungsten layer are buried in sequence in a plurality of wiring trenches
127
a
,
127
b
,
127
c
and a plurality of contact holes
128
a
,
128
b
,
128
c
,
128
d
. The barrier metal layer and the tungsten layer formed on the second interlayer insulating film
126
are removed by the chemical mechanical polishing (CMP) method.
Accordingly, in the memory cell region
101
, the bit line
106
made of a tungsten film is formed in the second interlayer insulating film
126
and also the bit line
106
is connected to the first contact plug
125
a
on the active region
103
via the contact hole
128
a
. Also, in the peripheral circuit region
102
, the first, second and third wirings
106
a
,
113
and
115
made of the tungsten film are formed in the second interlayer insulating film
126
. These wirings
106
a
,
113
and
115
are connected the impurity diffusion layers
112
a
,
112
b
and the lower wiring
114
via the contact holes
128
b
,
128
c
,
128
d
respectively.
A third interlayer insulating film
129
is formed on the bit line
106
, the wirings
106
a
,
113
,
115
and the second interlayer insulating film
126
.
Storage contact holes
109
reaching upper surface

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