Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-04
2002-11-19
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S407000, C257S412000, C257S915000
Reexamination Certificate
active
06483151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising an n-channel type insulated gate field effect transistor (herein after abbreviated as “MISFET”) and p-channel type MISFET with short gate lengths and relates to a method manufacturing the semiconductor device.
2. Description of the Related Art
MISFET has highly been integrated and improved to have high speed by making the configuration fine based on the scaling law.
In terms of example, it is required to make a gate insulating film as thin as 2 nm or thinner in a MISFET with 0.1 &mgr;m or shorter gate length. In the case a polycrystalline silicon film used as a constituent material for a gate electrode, a capacity is formed in the gate electrode in such a fine structure by depletion of impurities. Further, carrier quantization occurring in a channel inversion layer forms a capacity. Such capacities are formed in series in relation to the gate insulating film MOS capacity and therefore, the gate capacity is considerably lowered. It is possible to suppress the capacity attributed to the depletion among those capacities by using a metal for a constituent material of the gate electrode. In that case, in order to suppress the reaction of the gate metal film and the gate insulating film at the time of thermal treatment, it is necessary to form a barrier film with high conductivity between the gate metal film and the gate insulating film. A high melting point metal nitride such as titanium nitride, tungsten nitride or tantalum nitride may generally be used for the barrier film.
Further, the cross-section of the gate electrode and a diffusion layer is narrowed following the scaling to result in high sheet resistance of them and difficulty of fabrication of semiconductor device with high speed and excellent capability. In so far as the gate length is 0.12 &mgr;m, the countermeasure to deal with this problem is to employ salicide technique, that is, self-alignment silicide technique which involves process of forming a high melting point metal film e.g. a titanium film or a cobalt film on a polycrystalline silicon film and/or on a diffusion layer and making the metal film a silicide to form a high melting point metal silicide film and a high melting point metal silicide layer on the surface of them.
However, in the generation in which the gate length is narrowed to 0.1 &mgr;m or shorter, it has become hard to lower the resistance by the foregoing technique, because in an ultra-fine wire layer, the reaction of conversion into silicide is unreliable.
It becomes, therefore, effective to employ a metal film with a lower resistivity than that of a high melting point metal silicide film in order to lower the resistance of the gate electrode. Especially, in order to avoid increase of resistivity by post heating treatment, a high melting point metal film is required to be used as the metal film. The high melting point metal to be used is generally titanium, tungsten or tantalum. In order to suppress the reaction of the high melting point metal film of the gate electrode and the gate insulating film by the foregoing heating treatment, it is required to form a barrier film with a high conductivity between the high melting point metal film of the gate electrode and the gate insulating film.
The configuration of a complementary type MISFET comprising a high melting point metal film of the gate electrode and its fabrication method will be described in reference to
FIG. 1A
to
FIG. 1C
, which are cross-sectional views of manufacturing process steps of the semiconductor device.
First of all, an element separation region
402
is formed on the surface of a silicon substrate
401
and an n-type well region
403
and a p-type well region
404
are formed. A gate oxide film
405
is formed by thermal oxidation on the n-type well region
403
and the p-type well region
404
. A titanium nitride film
406
, a tungsten film
407
, and a hard mask film
408
of a first insulating film are successively formed on the whole surface (FIG.
1
A).
Then, the above described hard mask film
408
, tungsten film
407
, and titanium nitride film
406
are successively patterned by anisotropic etching to form a first gate electrode
409
with a layered structure of the titanium nitride film
406
and the tungsten film
407
on the surface of the n-type well
403
and to form a second gate electrode
410
with a layered structure of the titanium nitride film
406
and the tungsten film
407
on the surface of the p-type well
404
. Following that, an n-type source/drain extension region
411
and a p-type pocket region
412
are formed on the surface of the p-type well region
404
by ion implantation of n-type impurities and ion implantation of p-type impurities using the gate electrode
410
as a mask. In the same manner, a p-type source/drain extension region
413
and an n-type pocket region
414
are formed on the surface of the n-type well region
403
by ion implantation of p-type impurities and ion implantation of n-type impurities using the gate electrode
409
as a mask (FIG.
1
B).
Next, a second insulating film formed on the whole surface is etched back to form side wall spacers
415
covering the side faces of the gate electrodes
409
,
410
. Following that, an n
+
-source/drain region
416
is formed on the surface of the p-type well
404
by ion implantation of n-type impurities using the side wall spacers
415
and the gate electrode
410
as a mask. In the same manner, a p
+
-source/drain region
417
is formed on the surface of the n-type well
403
by ion implantation of p-type impurities using the side wall spacers
415
and the gate electrode
409
as a mask. Successively, for example, a titanium film is formed on the whole surface and made to be silicide to form a titanium silicide layer
418
respectively on the n
+
-source/drain region
416
and p
+
-source/drain region
417
(FIG.
1
C). After that, though being not illustrated, an interlayer insulating film or the like is formed on the whole surface to complete a conventional semiconductor device comprising a complementary type MISFET.
However, the absolute values of threshold voltage values of the foregoing n-channel type MISFET comprising the gate electrode
410
and the foregoing p-channel type MISFET comprising the gate electrode
409
are unfavorably increased as compared with those of an n-channel type MISFET comprising a gate electrode made of an n
+
-type polycrystalline silicon film and a p-channel type MISFET comprising a gate electrode made of a p
+
-type polycrystalline silicon film. That is attributed to that the Fermi level of a high melting point metal nitride generally exists between the lower end of the conduction band and the upper end of the filled band of silicon. The increase of the absolute value of the threshold voltage results in decrease of the operation speed of a complementary MISFET.
In general, the threshold voltage in a MISFET comprising a gate electrode made of polycrystalline silicon film is controlled by doping a surface part of a silicon substrate to be a channel region with an impurity to be a donor or an acceptor. However, such control of the threshold voltage by doping with an impurity is impossible for a MISFET having a gate electrode with a layered structure comprising a high melting point metal nitride film and a high melting point metal film.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide semiconductor devices each having a gate electrode structure capable of suppressing increase of the absolute value of the threshold voltage of at least either an n-channel or a p-channel in a complementary type MISFET.
Another object of the present invention is to provide methods of manufacturing the semiconductor device having such a gate electrode structure.
According to one feature of the present invention, there is provided a semiconductor device which comprises a silicon substrate, an n-type well and a p-type well separated f
Saito Yukishige
Wakabayashi Hitoshi
Kattan Muchin Zavis Rosenman
Prenty Mark V.
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