Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-07
2002-05-07
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S774000
Reexamination Certificate
active
06384441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same and, more particularly, to a semiconductor device having a self-align contact structure used in DRAM, etc. and to a method of manufacturing the same.
2. Description of the Prior Art
An element area in the semiconductor device is required to reduce, as the integration of the semiconductor device becomes higher. However, under the prior art, an alignment precision in the photolithography cannot be so improved as the requirement of the size reduction of the semiconductor device.
Thus, various techniques have been taken with the miniaturization of the semiconductor device. For example, the self-align contact used in the highly integrated semiconductor memory device such as DRAM (dynamic random access memory) is adopted.
In the self-align contact, the silicon nitride film is formed on the side faces of the gate electrode as the sidewall spacer. The self-align contact that is constructed by forming the sidewall spacer made of silicon nitride on the side faces of the gate electrode of the MOS transistor will be explained hereunder.
First, a manufacturing method of the structure shown in
FIG. 1A
will now be explained.
The active regions in the memory cell region
102
and the peripheral circuit region
103
on the silicon substrate
101
respectively are isolated by an isolation insulating film
104
. Then, the wells
105
,
106
are formed by implanting the impurity ion into predetermined active regions of the silicon substrate
101
and by using a mask.
Next, the gate insulating films
107
are formed in the active regions by the thermal oxidation method, and then a silicon film and a protection insulating film are formed sequentially by the chemical vapor deposition (CVD) method. Then, gate electrodes
108
a
,
108
b
are formed in the memory cell region
102
and the peripheral circuit region
103
by patterning a silicon film and a protection insulating film by virtue of the photolithography method. In this case, the gate electrodes
108
a
are formed in one active region in the memory cell region
102
at the predetermined interval.
In this case, upper surfaces of the gate electrodes
108
a
,
108
b
are covered with the protection insulating film
109
.
Next, steps to get the state shown in
FIG. 1B
will now be explained.
First, low impurity concentration portions of the impurity diffusion layers
110
a
,
110
b
are formed on both sides of the gate electrodes
108
a
,
108
b
on the silicon substrate
101
by ion-implanting the impurity into the active regions while using the gate electrodes
108
a
,
108
b
and the isolation insulating film
104
as a mask.
Then, a silicon nitride film for covering the gate electrodes
108
a
,
108
b
and the isolation insulating film
104
is formed on the silicon substrate
101
. Then, the silicon nitride film is left on both sides of the gate electrodes
108
a
,
108
b
as the sidewall spacers
11
a
,
111
b
by etching-back the silicon nitride film.
Then, high impurity concentration portions of the impurity diffusion layers
110
a
,
110
b
are formed by ion-implanting the impurity into the active regions while using the gate electrodes
108
a
,
108
b
and the sidewall spacers
111
a
,
111
b
as a mask.
Next, as shown in
FIG. 1C
, the first insulating film
112
and the second insulating film
113
for covering the gate electrodes
108
a
,
108
b
are formed in sequence. The silicon nitride film is formed as the first insulating film
112
, and the silicon oxide film containing the impurity, e.g., BPSG (Boro-Phospho Silicate Glass) is formed as the second insulating film
113
. The reason for forming the silicon nitride film under the BPSG is to prevent the diffusion of the impurity in BPSG into the silicon substrate
101
. The second insulating film
113
is heated to reflow and planarize its upper surface.
Then, as shown in
FIG. 1D
, the contact holes
113
a
to
113
c
are formed on the impurity diffusion layers
110
a
existing in the memory cell region
102
by patterning the first insulating film
112
and the second insulating film
113
by using the photolithography method. In this case, the second insulating film
113
in the memory cell region
102
is etched by the hydrofluoric acid, and the first insulating film
112
acts as an etching stopper. Also, the first insulating film
112
is etched by the phosphoric acid to expose the underlying impurity diffusion layer
110
b.
The widths of these contact holes
113
a
to
113
c
are decided by intervals between the sidewall spacers
111
a.
In this case, in one memory cell region
102
, the contact hole
113
a
formed in the center is used to connect the bit lines, and other two contact holes
113
b
,
113
c
are used to connect the capacitors.
Next, as shown in
FIG. 1E
, silicon plugs
114
a
to
114
c
are filled into the contact holes
113
a
to
113
c
. Then, the third insulating film
115
made of silicon oxide is formed on the second insulating film
113
and the plugs
114
a
to
114
c
. Then, the opening
116
is formed on the contact hole
113
a
for bit-line connection by patterning the third insulating film
115
by virtue of the photolithography method, and at the same time the contact hole
117
is formed on the impurity diffusion layer
110
b
by patterning the third insulating film
115
and the second insulating film
113
in the peripheral circuit region
103
by virtue of the photolithography method.
In forming the contact hole
117
, control of the depths of the opening
116
and the contact hole
117
can be facilitated since the first insulating film
112
and the plug
114
a
function as the etching stopper. Therefore, in order to expose the impurity diffusion layer
110
b
from the contact hole
117
, the first insulating film
112
must be etched via the contact hole
117
.
Here, the I—I sectional shape in
FIG. 1E
is shown in FIG.
3
A.
After this, as shown in
FIG. 1F
, the metal film is formed on the third insulating film
115
. Then, if this metal film is patterned, the bit line
118
connected to the plug
114
a
under the opening
116
is formed in the memory cell region
102
and also the wiring
119
connected to the impurity diffusion layer
110
b
via the contact hole
117
is formed in the peripheral circuit region
103
.
Then, although not shown particularly, the steps of forming a capacitor (not shown) on the memory cell region
102
will be carried out.
Other wirings of the gate electrode are formed in the peripheral circuit region
103
. In this case, in order to connect the wirings and the overlying wiring, the structure shown in
FIG. 4
is adopted.
Next, the steps of forming the structure shown in
FIG. 4
will be explained.
First, the device isolation insulating film
132
is formed on the surface of the silicon substrate
131
. Then, a plurality of gate electrodes
134
,
135
are formed in the memory cell region
102
and the peripheral circuit region
103
via the gate oxide film
133
respectively. At the same time, the first layer wiring
136
passing through over the device isolation insulating film
132
is formed in the peripheral circuit region
103
.
These gate electrodes
134
,
135
and the first layer wiring
136
have a double-layered structure that consists of a polysilicon film and a tungsten silicide film respectively. The protection insulating film
137
made of the silicon nitride film is formed thereon.
Then, the silicon nitride film is formed to cover the gate electrodes
134
,
135
, the first layer wiring
136
, and the silicon substrate
131
. Then, sidewall spacers
138
a
,
138
b
,
138
c
are left on both sides of the gate electrodes
134
,
135
and the first layer wiring
136
respectively by etching-back the silicon nitride film. The first layer wiring
136
has the structure that is extended from the gate electrode
135
to the device isolation insulating film
132
.
The impurity diffusion layers
139
a
,
139
b
serving as the source/drain are form
Hosoda Yukio
Ikemasu Shinichiroh
Sugiyama Koichi
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Wilson Allan R.
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