Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2000-11-22
2002-05-28
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S396000
Reexamination Certificate
active
06395612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which a ferroelectric substance material or a high dielectric constant material is mainly used as a capacitor insulating film and a method of manufacturing the same.
2. Statement of the Problem
Recently, development has been made in the area of semiconductor devices concerning a non-volatile memory having a capacitor device region in which a ferroelectric substance material, such as Pb(Zr,Ti)O
3
and SrBi
2
Ta
2
O
9
, having a hysteresis characteristic is used as a capacitor insulating film, and concerning a dynamic random access memory in which a capacitor device region has a large quantity of stored electric charges by using a high dielectric substance material, such as (Sr,Ba)TiO
3
, as the capacitor insulating film.
It has been known that deterioration of an insulating characteristic and a ferroelectric characteristic occurs in the dielectric substance, such as Pb(Zr,Ti)O
3
and (Sr,Ba)TiO
3
, used in the above semiconductor device, when the dielectric substance is subjected to a reduction atmosphere because the dielectric substance is formed by an oxide. In particular, when the dielectric substance is exposed to hydrogen, the device characteristics deteriorate critically. In the extreme case, peeling of an electrode may be caused to occur.
However, a hydrogen atmosphere inevitably is produced in a manufacturing process of the semiconductor device, such as a large scale integrated circuit (“LSI”). For example, a SiO
2
film which is used as an interlayer insulating film is generally formed by the use of a chemical vapor deposition (“CVD”) method. The reaction is represented by SiH
4
+O
2
→SiO
2
+2H
2
. This reaction formula indicates that the hydrogen is generated as a reaction product. Further, the CVD of tungsten (“W”) tends to be widely used to embed a contact hole having a large aspect ratio as the device size becomes small. In this case, the W is deposited by the reaction which is represented by 2WF
6
+3SiH
4
→2W+3SiH
4
+6H
2
. This reaction formula indicates that the reaction is carried out in a very strong reduction atmosphere. In addition, an annealing process is performed in an atmosphere containing the hydrogen to ensure the characteristic of a MOS transistor after the formation of an Al wiring pattern.
Means for preventing the dielectric capacitor from deteriorating due to the hydrogen has been adopted in several semiconductor devices, as known in the art. For example, disclosure is made in Japanese Unexamined Patent Publication No. H4-102367 of a semiconductor device, illustrated in
FIG. 27
, which has a TiN film or a TiON film formed on an interlayer insulating film
16
of a capacitor portion
19
as a hydrogen barrier film
17
. In the structure illustrated in
FIG. 27
, a device isolation oxide film
2
, an interlayer insulating film
6
, a lower electrode
8
, a capacitor insulating film
9
, an upper electrode
10
, an interlayer insulating film
13
, a wiring layer
14
, an interlayer insulating film
16
, and a hydrogen barrier film
17
are successively deposited on a silicon substrate
1
in this order. Further, a gate electrode
5
is formed on a gate oxide film
4
between impurity diffusion regions
3
in the silicon substrate
1
.
Alternatively, AIN or Ti
3
N
4
is formed on an upper electrode
10
of a capacitor portion
19
as a hydrogen barrier film
11
in the structure illustrated in
FIG. 28
in the case of a dielectric memory which is disclosed in Japanese Unexamined Patent Publication No. H7-111318. On the other hand, Si
3
N
4
is formed on the entire surface of the device as a hydrogen barrier film
12
in the structure illustrated in FIG.
29
.
More specifically, a device isolation oxide film
2
, an interlayer insulating film
6
, a lower electrode
8
, a capacitor insulating film
9
, an upper electrode
10
, a hydrogen barrier film
11
, an interlayer insulating film
13
and a wiring layer
14
are successively deposited on a silicon substrate
1
in this order in the structure illustrated in FIG.
28
. Further, a gate electrode
5
is formed on a gate oxide film
4
between impurity diffusion regions
3
in the silicon substrate
1
. In the structure illustrated in
FIG. 29
, a device isolation oxide film
2
, an interlayer insulating film
6
, a lower electrode
8
, a capacitor insulating film
9
, an upper electrode
10
, a hydrogen barrier film
11
, a hydrogen barrier film
12
, an interlayer insulating film
13
and a wiring layer
14
are successively deposited on a silicon substrate
1
in this order. In this case, the hydrogen barrier film
12
is formed to cover the lower electrode
8
, the capacitor insulating film
9
, the upper electrode
10
and the hydrogen barrier film
11
. In addition, a gate electrode
5
is formed on a gate oxide film
4
between impurity diffusion regions
3
in the silicon substrate
1
.
Where the hydrogen barrier film
17
is formed on the interlayer insulating film
16
of the capacitor portion
19
like the conventional semiconductor device illustrated in
FIG. 27
, the hydrogen barrier film
17
must cover the capacitor portion
19
with a space area of several microns or more from the capacitor portion
19
to prevent the invasion of the hydrogen from a lateral direction. However, cell area has been reduced with the high integration of memories, and the cell area of a highly integrated memory of 256 Megabit or more is 1 &mgr;m
2
or less, as disclosed in Nikkey Micro Device, March 1995, at page 31. In such a case, the area of the hydrogen barrier film
17
over the capacitor portion
19
must be equal to or less than the cell area. Consequently, the invasion of the hydrogen from the lateral direction cannot sufficiently be prevented. In addition, the conventional semiconductor device is not effective at all for avoiding deterioration of the capacitor portion
19
due to the hydrogen where CVD of W is used for the wiring layer, since the hydrogen barrier film is formed over-the wiring layer
14
.
Further, the other conventional semiconductor device illustrated in
FIG. 28
is not effective at all for avoiding the invasion of the hydrogen from the side portion. In addition, the characteristic of the MOS transistor which is ensured by the hydrogen anneal is hindered after the formation of the Al wiring pattern in the other conventional semiconductor device illustrated in
FIG. 29
, since the Si
3
N
4
film is formed for the entire surface of the device. In this case, the hindrance of the hydrogen annealing effect from the formation of Si
3
N
4
film has been widely known as described in PROCEEDINGS OF THE SYMPOSIUM ON SILICON NITRIDE THIN INSULATING FILMS, 1983, pages 94 to 110.
3. Solution to the Problem
In the semiconductor device according to this invention, the capacitor portion is directly covered with the hydrogen barrier film and further, the hydrogen barrier film, except for a part covering the capacitor portion, is removed. Consequently, the characteristic of the MOS transistor is not adversely affected, and the deterioration of the capacitor portion can be effectively avoided.
According to this invention, there is provided a semiconductor device which has a capacitor portion including a ferroelectric substance material or a high dielectric constant material as a capacitor insulating film. The capacitor portion is covered with a hydrogen barrier film, and the remaining portion excepting the capacitor portion is uncovered with the hydrogen barrier film.
A method of manufacturing the semiconductor device according to this invention includes a step of forming the capacitor portion comprising a lower electrode, a capacitor insulating film of ferroelectric substance material or high dielectric constant material and an upper electrode, a step of forming the hydrogen barrier film for covering the capacitor portion, and a step of removing a part of the hydrogen barrier film by etching.
A feature of the invention is a semiconductor device having
Chaudhuri Olik
Patton & Boggs LLP
Peralta Ginette
Symetrix Corporation
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