Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2000-02-07
2002-01-08
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S692000, C438S928000, C438S959000, C438S977000, C257S668000
Reexamination Certificate
active
06337257
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device capable of being suitably used for a surface-mounted package such as a TCP (tape carrier package) where a semiconductor chip is mounted on a carrier tape, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, with improving performance and decreasing size and weight of electronic apparatuses, LSI (large scale integration) packages are required to have more pins, finer pitches, smaller sizes and smaller thicknesses. As a semiconductor device highly likely to realize these requirements, a tape carrier package (abbreviated as TCP) which is a surface-mounted semiconductor device is frequently used. To further reduce the thickness of this semiconductor device, it is necessary to reduce the thickness of the semiconductor chip mounted on the chip substrate. Most semiconductor devices are used as liquid crystal driving circuits also called liquid panel drivers, and are directly connected to liquid crystal panels. By reducing the thickness of such semiconductor devices, the thickness of the liquid crystal panels on which the semiconductor devices are mounted can be reduced, and therefore, the liquid crystal panels being reduced in thickness are mounted. For example, the thickness of electronic apparatuses such as portable personal computers also called notebook computers and portable word processors can be also reduced.
In reducing the thickness of the semiconductor devices, for a semiconductor chip with a low aspect ratio between the chip length and the chip width where the chip width is not less than 1.5 mm and the chip length is not more than 16 mm, the semiconductor chip is ground until the thickness thereof becomes approximately 400 &mgr;m to manufacture a semiconductor device. In connection with grinding a semiconductor chip having such a low aspect ratio, in preprocessing for formation of the semiconductor chips from a semiconductor wafer on one surface of which are formed semiconductor elements, another surface of the wafer, opposite to the one surface, is ground to reduce the thickness of the wafer to approximately 400 &mgr;m, and thereafter using the semiconductor wafer having a thickness of approximately 400 &mgr;m, assembly is performed without applying any processing to the ground surface to manufacture the semiconductor device.
FIG. 8
is a cross-sectional view showing a typical prior art semiconductor device
1
. In the above-described semiconductor device
1
, no die pad is provided, but a semiconductor chip
3
elongated in a direction perpendicular to the plane of
FIG. 8
is only covered with an encapsulating resin
2
and no mechanical reinforcement is provided. For this reason, the semiconductor chip
3
itself is responsible for the overall mechanical strength of the semiconductor device
1
. Therefore, thickness reduction of the semiconductor chip
3
reduces the mechanical strength of the semiconductor device
1
. The semiconductor device
1
tends to increase in the chip length in the direction of the length perpendicular to the plane of
FIG. 8
like an SST (super slim TCP). The chip length is, for example, approximately 20 mm. The semiconductor chip
3
tends to decrease in the width in the horizontal direction of
FIG. 8
conversely to the length thereof. The chip width is, for example, not more than 1 mm. Thus, the mechanical strength of the semiconductor chip
3
tends to decrease.
The semiconductor chip
3
has an input side wiring
4
and an output side wiring
5
, and is connected to an inner lead
7
of a carrier tape
6
made of a polyimide base material by inner lead bonding (abbreviated as ILB). The input side wiring
4
and the output side wiring
5
are covered with solder resists
8
and
9
. A bump
11
is formed at the terminal of a surface
10
of the semiconductor chip
3
where semiconductor elements are formed. An end of the inner lead
7
is connected to the bump
11
. The semiconductor chip
3
has grinding scratches
14
including cracks
13
caused by grinding for flattening the semiconductor wafer, on another surface
12
opposite to the surface
10
where the semiconductor elements are formed, and has dicing scratches
16
of side surfaces
15
of the chip caused by dicing the semiconductor wafer.
When the width of the semiconductor chip
3
is not less than 1.5 mm where the mechanical strength of the semiconductor chip
3
is comparatively high, grinding of the surface
12
causes no problem of strength. However, when the width is approximately 1.0 mm, chip cracking occurs when the semiconductor device
1
is assembled and when the semiconductor device
1
is mounted on the mounting substrate of an electronic apparatus. With respect to such cracking of the chip of the semiconductor device
1
, the inventor of this application has verified that in addition to the reduction in mechanical strength due to the insufficient cross section of the semiconductor chip
3
itself because of the grinding of the surface
12
, the grinding scratches
14
caused by grinding and the dicing scratches
16
caused in the dicing process are main factors of the reduction in the mechanical strength of the semiconductor chip
3
.
When the mechanical strength of the semiconductor chip
3
is low as described above, chip cracking occurs in the ILB process including a process in which an external force due to contact with another semiconductor chip acts on the semiconductor chip
3
in the assembling process, and in the marking process. Moreover, when the semiconductor device
1
is mounted on the mounting substrate, the semiconductor device
1
where the semiconductor chip
3
having been ground is mounted cracks with a slight external force, so that the electronic apparatus does not function.
FIG. 9
is a cross-sectional view showing the structure for measuring the mechanical strength of the semiconductor device
1
. In the measurement of the mechanical strength of the semiconductor chip
3
, the semiconductor device
1
in which the semiconductor chip
3
was ground to a thickness of 400 &mgr;m and the grinding scratches
14
were formed on the surface
12
of the semiconductor chip
3
with a width of 1.2 mm in a direction (horizontal direction of
FIG. 9
) vertical to the direction of the chip length was fixed so that both ends in the direction of the width of the semiconductor chip
3
were supported by a stage
17
, and the central part in the direction of the width of the semiconductor chip
3
was pressed by a jig
18
from above. The mechanical strength of the semiconductor chip
3
was only 1.47 N/cm (=150 gf/cm). The inventor of this application has verified that when 3&sgr; is added, the semiconductor chip can crack with a pressure F=0N.
FIGS. 10A
to
10
C are views of assistance in explaining the difference in grinding scratches among the positions of cutting of the semiconductor chip
3
from a semiconductor wafer
19
.
FIG. 10A
is a plan view showing the semiconductor wafer
19
having been surface-ground.
FIG. 10B
is a perspective view showing grinding scratches
14
a
and dicing scratches
16
a
when a semiconductor chip
3
a
cut from a first area
20
of the semiconductor wafer
19
is mounted on a chip substrate
6
.
FIG. 10C
is a perspective view showing grinding scratches
14
b
and dicing scratches
16
b
when a semiconductor chip
3
b
cut from a second area
21
of the semiconductor wafer
19
is mounted on the chip substrate
6
.
The grinding scratches
14
formed after the grinding of the surface
12
of the semiconductor wafer
19
are spiral as shown in
FIG. 10A
, and the direction of the grinding scratches
14
formed on the surface
12
of the semiconductor chip
3
differs according to the cutting position on the semiconductor wafer
19
. When the semiconductor chip
3
a
cut by dicing from the first area, represented by reference numeral
20
, of the semiconductor wafer
19
shown in
FIG. 10A
is assembled on the chip substrate
6
without any processing bein
Elms Richard
Nixon & Vanderhye P.C.
Pyonin Adam
Sharp Kabushiki Kaisha
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