Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1999-01-20

2002-03-19

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S104000, C438S302000, C438S525000

Reexamination Certificate

active

06358783

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a MOS (Metal Oxide Semiconductor) field effect transistor (hereinafter referred to as “SOI-MOSFET”) formed in a semiconductor layer on an insulator such as an insulator substrate and a method of manufacturing the same, and, more particularly, to a technique for improving withstand voltage and current driving characteristics between source and drain regions.
2. Description of the Background Art
FIG. 1
is a sectional view of a SOI-MOSFET as a first conventional example. Referring to
FIG. 1
, the SOI-MOSFET includes an insulator layer
2
formed on a silicon substrate
1
and a silicon layer
3
formed on insulator layer
2
. A channel forming region
6
having a low concentration of p-type impurities (10
16
-10
17
/cm
3
, for example) is formed in silicon layer
3
, and an additional source region
7
a
and an additional drain region
8
a
having a concentration of n-type impurities (10
17
-10
18
/cm
3
, for example) are formed respectively in contact with the left and right sides of channel forming region
6
. A source region
7
b
and a drain region
8
b
having a high concentration of n-type impurities concentration (10
19
-10
21
//cm
3
, for example) are formed respectively adjacent to additional source region
7
a
and additional drain region
8
a.
A gate insulating film
4
is formed on channel forming region
6
, and a gate electrode
5
is formed on gate insulating film
4
. Sidewalls
13
are provided on the sidewalls of gate electrode
5
on additional source region
7
a
and additional drain region
8
a
. Silicon layer
3
and gate electrode
5
are covered with an interlayer insulating film
9
. Contact holes
10
a
,
10
b
are provided in interlayer insulating film
9
, and corresponding conductors, i.e. a source electrode
11
and a drain electrode
12
in this case, are formed in respective contact holes
10
a
,
10
b.
If positive voltage is applied to gate electrode
5
in a SOI-MOSFET constituted as described above, n-type carriers (electrons) are induced to the upper part of p-type channel forming region
6
, and the upper part is inverted to be the same n-type as additional source region
7
a
, additional drain region
8
a
, source region
7
b
, and drain region
8
b
. Accordingly, current can flow between source region
7
b
and drain region
8
b
. In addition, the concentration of the n-type carriers induced to upper part of channel forming region
6
changes in accordance with the gate voltage, so that it is possible to control the current flowing in channel forming region
6
with the gate voltage. This is the operation principle of the MOSFET.
The reason why additional source region
7
a
and additional drain region
8
a
were formed respectively adjacent to source region
7
b
and drain region
8
b
in the first conventional thin film SOI-MOSFET having the above-described structure is as described in the following.
In a case where it is a thin film SOI-MOSFET having silicon layer
3
of approximately 300 Å-1500 Å, even if additional source region
7
a
and additional drain region
8
a
are not formed, the whole of channel forming region
6
is easily made to be a depletion layer by applying voltage to gate electrode
5
, and the potential of the channel forming region is also controlled by the gate electrode, so that so-called punch through or short channel effect is reduced. Here, “punch through” is a phenomenon that a depletion layer extending from drain region
8
b
into channel forming region
6
reaches to source region
7
b
, the electric barrier between source region
7
b
and channel
6
is lowered, and the channel current is suddenly increased by it. “Short channel effect” is a phenomenon that when the gate length is short, the gate threshold voltage becomes extremely low.
However, if the whole of channel forming region
6
is completely depleted, the potential in channel forming region
6
becomes higher than that in the case of a conventional bulk MOSFET. Accordingly, the electric barrier between source region
7
b
and channel forming region
6
is lowered, and holes generated by so-called impact ionization, a phenomenon that highly accelerated electrons collide with a lattice in the vicinity of drain region
8
b
and cause electrons and holes to be generated, come to be temporarily stored in channel forming region
6
. As a result, the potential in channel forming region
6
is further raised, and electrons are suddenly injected from source region
7
b
into channel forming region
6
. Specifically, in a case where additional source region
7
a
and additional drain region
8
a
are not formed in a thin film SOI-MOSFET expected as a short channel MOSFET, the withstand voltage between the source and the drain tends to be lowered.
FIG. 4A
shows the drain current—drain voltage characteristics of the thin film SOI-MOSFET in this case.
In order to prevent such lowering of the withstand voltage between the source and the drain, a so-called LDD (Lightly Doped Drain) structure is constituted by providing a low second conductivity-type additional drain region
8
a
between drain region
8
b
and channel forming region
6
in a normal thin film SOI-MOSFET such as the first conventional example described above to reduce the electric field in the vicinity of drain region
8
b
and prevent storage of holes caused by impact ionization so that the withstand voltage between the source and the drain is enhanced. Now, a method of manufacturing the above-described first conventional thin film SOI-MOSFET will be described with reference to
FIGS. 2A-2E
.
First, referring to
FIG. 2A
, a silicon layer
3
is formed on a silicon substrate
1
with an insulator layer
2
interposed therebetween. Specific manufacturing methods in this case normally include SIMOX (Separation by Implanted Oxygen) in which oxygen ions are implanted in silicon substrate
1
and a silicon oxide film is formed directly in silicon substrate
1
.
Next, silicon layer
3
is patterned into a shape of an island, and p-type impurities such as boron are introduced by an ion implantation process or the like to make the concentration 10
16
-10
17
/cm
3
, for example, to form a channel forming region
6
(FIG.
2
B).
A gate insulating film
4
is formed on silicon layer
3
by a thermal oxidation process or the like, and a gate electrode material such as polycrystalline silicon is deposited by a CVD method. A resist
14
is patterned on the polycrystalline silicon by a photolithography process, and the polycrystalline silicon is etched using the resist
14
to form a gate electrode
5
.
Next, n-type impurities such as phosphorus are introduced into silicon layer
3
using gate electrode
5
and resist
14
as a mask to make the concentration 10
17
-10
18
/cm
3
to form an additional source region
7
a
and an additional drain region
8
a
(FIG.
2
C).
Next, a silicon oxide film
13
a
is deposited by a CVD method (FIG.
2
D), anisotropic etching is carried out on silicon oxide film
13
a
by a reactive ion etching process to form a sidewall spacer
13
on the sidewalls of gate electrode
5
. Next, n-type impurities such as phosphorus or arsenic are ion-implanted in silicon layer
3
using gate electrode
5
and sidewall spacer
13
as a mask, and a source region
7
b
and a drain region
8
b
are formed to have a concentration of 10
19
-10
21
/cm
3
, for example (FIG.
2
E).
An interlayer insulating film
9
is formed, then contact holes
10
a
,
10
b
are formed by a reactive ion etching process, for example, and conductive interconnection layers
11
,
12
including aluminum or the like are formed to complete the structure illustrated in FIG.
1
.
As described above, the above first conventional thin film SOI-MOSFET has the concentration of additional source region
7
a
and additional drain region
8
a
lowered to approximately 10
17
/cm
3
in order to enhance the withstand voltage between the source and the drain by electric field reduction. Therefore, the

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