Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-06-22
2002-03-19
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S149000, C438S290000, C438S960000
Reexamination Certificate
active
06358815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOSFET structure and a method of manufacturing the same.
2. Description of the Background Art
FIG. 21
is a cross section showing a background-art MOSFET structure using a bulk substrate. A multi-layered structure consisting of a gate oxide film
102
and a gate electrode
103
layered in this order is selectively formed on an upper surface of a silicon substrate
101
. Sidewalls
104
are formed on side surfaces of the gate oxide film
102
and the gate electrode
103
. A source region
105
and a drain region
106
are selectively formed in the upper surface of the silicon substrate
101
.
Applying a voltage to the silicon substrate
101
from its backside makes a potential of the silicon substrate
101
fixed and ensures a stable operation of a transistor and a circuit against variation in potential of the gate electrode
103
and the source and drain regions
105
and
106
.
FIG. 22
is a cross section showing a background MOSFET using an SOI (Silicon On Insulator) substrate. The SOI substrate has a silicon substrate
110
, a buried oxide film
111
and a silicon layer
112
. Further, like the structure of
FIG. 21
, the gate oxide film
102
, the gate electrode
103
and the sidewalls
104
are selectively formed on the upper surface of the silicon layer
112
. The source region
105
and the drain region
106
are selectively formed in the upper surface of the silicon layer
112
. A body region
113
is formed between the source region
105
and the drain region
106
.
An electric line of force from the source region
105
and the drain region
106
is terminated at the silicon substrate
110
through the buried oxide film
111
. Therefore, junction capacitance between the source and drain regions
105
and
106
and the silicon substrate
110
becomes smaller and a current to charge this junction capacitance during an operation of a transistor is reduced, to ensure a faster operation and lower power consumption.
The background-art MOSFETs as above, however have the following problems.
First, the MOSFET using a bulk substrate, as compared with the MOSFET using an SOI substrate, disadvantageously operates more slowly and consumes larger power. Since the width W
100
of a depletion layer
120
created by a pn junction between the source and drain regions
105
an
106
and the silicon substrate
101
is narrow, the junction capacitance between the source and drain regions
105
and
106
and the silicon substrate
101
becomes larger. As a result, it is necessary to charge the larger junction capacitance when the potentials of the source region
105
and the drain region
106
are varied during the operation of the transistor.
Next, the MOSFET using an SOI substrate, as compared with the MOSFET using a bulk substrate, disadvantageously performs more unstable operation. As shown in
FIG. 22
, the body region
113
is in an electrical floating state. Therefore, the potential of the body region
113
varies with variation in potential of the gate electrode
103
, the source region
105
and the drain region
106
. Such a variation in potential of a body region is specifically described in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 7, JULY 1998, pp 1479-1484, “Analysis of Delay Time Instability According to the Operating Frequency in Field Shield Isolated SOI Circuit” S. Maeda et al. (document 1). Specifically, the potential of the body region transiently varies and with this variation of potential, the characteristics of the transistor transiently varies, causing an unstable circuit operation (see
FIG. 7
of the document 1).
Further, the document 1 shows a structure to fix the potential of the body region in order to ensure a stable circuit operation (see
FIGS. 1 and 2
of the document 1). Since the structure of the document 1, however, needs a field shield isolated structure to fix the potential of the body region, a manufacturing process therefor becomes more complicate and requires longer time. To form the field shield isolated structure, it is necessary to form a field shield isolation layer which is not formed in a usual MOSFET using a bulk substrate. That needs a change of layout pattern between this MOSFET of the document 1 and the usual MOSFET using a bulk substrate.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a substrate; a porous layer formed on the substrate; a semiconductor layer formed on the porous layer; and a semiconductor element formed in the semiconductor layer.
Preferably the porous layer is a porous silicon layer.
According to a second aspect of the present invention, the semiconductor device comprises: a first semiconductor region of a first conductivity type; a first porous layer formed inside the first semiconductor region as a buried layer; and a source/drain region of a second conductivity type different from the first conductivity type, selectively formed in an upper surface of the first semiconductor region, and in the semiconductor device of the second aspect, a depletion layer created in a junction between the first semiconductor region and a bottom surface of the source/drain region can exist in the first porous layer.
Preferably, the first porous layer is a porous silicon layer.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the first semiconductor region has an epitaxial layer in its upper portion.
According to a fourth aspect of the present invention, in the semiconductor device of the second aspect, the bottom surface of the source/drain region is located adjacently above an upper surface of the first porous layer.
According to a fifth aspect of the present invention, in the semiconductor device of the second aspect, the bottom surface of the source/drain region is located adjacently below an upper surface of the first porous layer.
According to a sixth aspect of the present invention, in the semiconductor device of the second aspect, the first semiconductor region has a high-concentration impurity region of the first conductivity type which is located deeper than the first porous layer.
According to a seventh aspect of the present invention, the semiconductor device of the second aspect further comprises: a second semiconductor region of the second conductivity type formed adjacently to the first semiconductor region; a second porous layer formed inside the second semiconductor region as a buried layer, being connected to the first porous layer; and a trench-type isolation structure formed in an interface between the first semiconductor region and the second semiconductor region, extending deeper than bottom surfaces of the first and second porous layers from the upper surface of the first semiconductor region and an upper surface of the second semiconductor region.
The present invention is also directed to a method of manufacturing a semiconductor device. According to an eighth aspect of the present invention, the method comprises the steps of: (a) forming a first semiconductor region of a first conductivity type in which a first porous layer is formed as a buried layer; and (b) selectively forming a source/drain region of a second conductivity type different from the first conductivity type in an upper surface of the first semiconductor region, wherein a depletion layer created in a junction between the first semiconductor region and a bottom surface of the source/drain region can exist in the first porous layer.
Preferably, the first porous layer is a porous silicon layer.
Preferably, the porous silicon layer is formed by anodization.
According to a ninth aspect of the present invention, in the method of the eighth aspect, the step (a) has the steps of (a-1) forming the first porous layer; and (a-2) forming an epitaxial layer on an upper surface of the first porous l
Mitsubishi Denki & Kabushiki Kaisha
Tsai Jey
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