Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2011-08-09
2011-08-09
Blum, David S (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257SE21403, C257SE21409
Reexamination Certificate
active
07994538
ABSTRACT:
A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.
REFERENCES:
patent: 2006/0138398 (2006-06-01), Shimamune et al.
patent: 2007/0264810 (2007-11-01), Kim et al.
patent: 2004-039831 (2004-02-01), None
patent: 2006-186240 (2006-07-01), None
patent: 10-0722939 (2007-05-01), None
Chinese Office Action dated Dec. 11, 2009, issued in corresponding Chinese Patent Application No. 2008101701751.
Blum David S
Fujitsu Semiconductor Limited
Westerman Hattori Daniels & Adrian LLP
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