Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-30
2001-12-25
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000, C257S368000, C257S379000, C257S380000, C257S536000, C257S538000
Reexamination Certificate
active
06333542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an SRAM (Static Random Access Memory) cell being capable of securing high reliability and a method for manufacturing the same.
2. Description of the Related Art
As a method of decreasing an occupied area of a chip by an SRAM, a method of constituting a load resistor (resistance element) by a high-resistance polycrystalline silicon film having a high resistance exists. Such a SRAM cell is called a high-resistance polycrystalline silicon load resistor type cell. The resistance element constituted by a high-resistance polycrystalline silicon film is stacked on the upper layer of MOS transistors constituting the SRAM cell. In this manner, an occupied area by the SRAM is reduced.
FIG. 1
is an equivalent circuit diagram showing the arrangement of an SRAM cell. In the SRAM cell, a flip-flop connected between a power supply Vcc and a ground potential Vss is arranged. The flip-flop is constituted by driver transistors Tr
1
and Tr
2
, load resistors R
1
and R
2
, and a cross wirings. A connection point of one terminal of the load resistor R
1
, one terminal of the driver transistor Tr
1
, and the gate of the driver transistor Tr
2
serves as a storage node Q
1
. Similarly, a connection point of one terminal of the load resistor R
2
, one terminal of the driver transistor Tr
2
, and the gate of the driver transistor Tr
1
serves as a storage node Q
2
. When data are held in the SRAM cell, data “High” and data “Low” are stored in each of the storage nodes.
One terminal of an access transistor Tr
3
is connected to the storage node Q
1
, and one terminal of an access transistor Tr
4
is connected to the storage node Q
2
. A word line WL is connected to the gates of the access transistors Tr
3
and Tr
4
. A bit line BL
1
is connected to the other terminal of the access transistor Tr
3
, and a bit line BL
2
is connected to the other terminal of the access transistor Tr
4
.
The resistance value of a supply portion of the power supply Vcc, the resistance value of the cross wiring between the storage node Q
1
and the driver transistor Tr
2
, and the resistance value of the cross wiring between the storage node Q
2
and the driver transistor Tr
1
are preferably set to be approximately several K&OHgr;/sq. or less to secure high reliability for the following reason. When the resistance value of the cross wirings exceeds the value described above, data transfer is delayed during data inversion of the memory cell, and a high-speed stable operation of the memory cell is hindered.
On the other hand, the load resistors R
1
and R
2
require resistances of about several G&OHgr; to several T&OHgr; or more because the SRAM cell is demanded to have a low power consumption. For example, when data “High” is stored in the storage node Q
1
, the driver transistor Tr
2
is set in an ON state, and a through current flows from the power supply Vcc to the ground potential Vss through the load resistor R
2
and the driver transistor Tr
2
. At this time, when the resistance value of the load resistor R
2
is lower than the required resistance value, an excessive current flows from the power supply Vcc to the ground potential Vss as a standby current. Therefore, a power consumption of the SRAM increases. A similar operation is also performed when the data “High” is stored in the storage node Q
2
. For this reason, the load resistors R
1
and R
2
require extremely high resistances.
The high-resistance polycrystalline silicon load resistor type cell is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-219494.
FIG. 2
is a sectional view showing a conventional semiconductor device described in Japanese Patent Application Laid-Open No. 9-219494.
A field oxide film
202
functioning as an element isolation region is formed at the surface of a semiconductor substrate
201
. A gate oxide film
203
is formed on the semiconductor substrate
201
. The field oxide film
202
and the gate oxide film
203
are shown as the same layer for descriptive convenience. A channel region is formed at the surface of the semiconductor substrate
201
below the gate oxide film
203
. Source-drain regions (not shown) are formed on both the side portions of the channel region. A gate electrode
204
is formed on the gate oxide film
203
. A driver MOS transistor having the gate electrode
204
, the gate oxide film
203
, the channel region, and the source-drain regions is formed.
In addition, in a region, at the surface of the semiconductor substrate
201
, in which the gate electrode
204
is not formed, an N
+
-diffusion layer
207
, which is one of source-drain regions of an access MOS transistor, is selectively formed. An interlayer insulating film
208
in which a common contact hole
209
is provided is formed on the entire surface of the resultant structure. The common contact hole
209
is formed in a region corresponding to any one of the storage nodes of the SRAM cell. A pad polycrystalline silicon layer
210
is formed in the common contact hole
209
and selectively on the interlayer insulating film
208
. The pad polycrystalline silicon layer
210
is constituted by a low-resistance polycrystalline silicon film. The pad polycrystalline silicon layer
210
is formed in a region corresponding to the storage node and the cross wiring between the storage node and the driver transistor connected thereto. A resistance polycrystalline silicon layer
212
is selectively formed on the pad polycrystalline silicon layer
210
and the interlayer insulating film
208
. The resistance polycrystalline silicon layer
212
is constituted by a high-resistance polycrystalline silicon film. The resistance polycrystalline silicon layer
212
is formed in a region corresponding to a resistance element formed on the MOS transistor, i.e., a load resistor.
Of the resistance polycrystalline silicon layer
212
, a portion directly formed on the interlayer insulating film
208
on the MOS transistor functions as the high-resistance load resistor. The length of the portion is called a resistor length. As the resistor length increases, the resistance of the load resistor in the SRAM cell increases.
The SRAM cell is manufactured in the following manner.
FIGS. 3A
to
3
F are sectional views sequentially showing the steps in a method of manufacturing the conventional semiconductor device.
As shown in
FIG. 3A
, the field oxide film (silicon oxide film)
202
serving as an element separation region is formed at the surface of the semiconductor substrate
201
. A silicon oxide film and a tungsten polycide film are sequentially stacked. These films are patterned to form the gate oxide film
203
and the gate electrode
204
. The N
+
-diffusion layer
207
serving as an impurity diffusion layer of an access transistor is selectively formed at the surface of the semiconductor substrate
201
. At this time, source-drain regions (not shown) of a driver transistor are formed.
Thereafter, as shown in
FIG. 3B
, the interlayer insulating film
208
is formed on the entire surface of the resultant structure, and a mask for opening a contact hole is formed on the interlayer insulating film
208
by a resist
241
. The common contact hole
209
is formed in the interlayer insulating film
208
, and the resist
241
is removed.
Thereafter, as shown in
FIG. 3C
, the pad polycrystalline silicon layer
210
constituted by a low-resistance polycrystalline silicon film is formed on the entire surface of the resultant structure. In addition, a resist
242
having a predetermined shape is formed on the pad polycrystalline silicon layer
210
. In general, an impurity is implanted in the pad polycrystalline silicon layer
210
at a high concentration to reduce the resistance thereof.
Thereafter, the pad polycrystalline silicon layer
210
is etched by using the resist
242
as a patterning mask. Then, as shown in
FIG. 3D
, the resist
242
is removed.
Thereafter, as shown in
FIG. 3E
, the resistance polycrystalline silicon l
Lee Eddie
Lee Eugene
NEC Corporation
Sughrue & Mion, PLLC
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2601835