Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-08-22
2001-12-11
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C257S623000, C257S773000
Reexamination Certificate
active
06329671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the same, and more specifically, to a method of dividing a semiconductor wafer into semiconductor chips and to the structure of the semiconductor chip obtained from the same.
2. Description of the Background Art
Presently, a dicing method is mainly used for dividing a compound semiconductor wafer into semiconductor chips. Now, a method of dividing the semiconductor wafer using the dicing method will be described.
FIGS. 28
to
30
are schematic plan views sequentially showing the steps of the method of dividing the semiconductor wafer using the dicing method. In addition,
FIGS. 31
to
33
are schematic cross sectional views taken along the lines G—G in
FIGS. 28
to
30
.
Referring firstly to
FIGS. 28 and 31
, a plurality of functional devices
3
are arranged and formed spaced apart from one another by a dicing line region
2
on the surface of a semiconductor layer
1
of a semiconductor wafer
4
c
. Thereafter, the back surface of semiconductor layer
1
is polished by means for example of a polishing method, so that the thickness of semiconductor wafer
4
c
is made as small as 400 &mgr;m or less. On the back surface of the thin semiconductor layer
1
, a metal layer
5
is formed with a thickness of 1 &mgr;m or less as a layer for solder adhesion in die bonding a semiconductor chip to a package.
Referring to
FIGS. 29 and 32
, metal layer
5
on the back surface of semiconductor wafer
4
c
, thus prepared, is applied to an expand sheet
23
which is expandable. Thereafter, semiconductor wafer
4
c
is cut along dicing line region
2
by a dicing saw.
Referring to
FIGS. 30 and 33
, by cutting semiconductor wafer
4
c
, it is divided into separate semiconductor chips
10
c
. Then, expansion of expand sheet
23
increases the spaces between separate semiconductor chips
10
c
, thus facilitating removal (recovery) of separate semiconductor chips
10
c.
It is noted that grooves
23
a
are formed to some extent in expand sheet
23
during dicing of semiconductor wafer
4
c.
FIG. 34
is a perspective view schematically showing the structure of semiconductor chip
10
c
which is obtained from the dicing. In addition,
FIGS. 35 and 36
are schematic cross sectional views taken along the lines H—H and I—I in FIG.
34
.
Referring to
FIGS. 34
to
36
, for separate semiconductor chip
10
c
obtained from the above mentioned dicing, functional device
3
is formed on the surface of semiconductor layer
1
, and a dicing line region
2
a
, on which the device has not been formed, surrounds the periphery of functional device
3
. Metal layer
5
is also formed on the entire back surface of semiconductor layer
1
.
Among the above mentioned compound semiconductor devices, especially in the device such as a high output FET (Field Effect Transistor) which requires thermal resistance reduction, the thickness of semiconductor wafer
4
c
must be made as small as 50 &mgr;m or less, as shown in
FIGS. 28 and 31
. With such a small thickness as 50 &mgr;m or less, semiconductor wafer
4
c
may crack during handling. Then, metal layer
5
with a thickness of 1 &mgr;m or more must be formed on the back surface of semiconductor wafer
4
c
to reinforce it.
However, if dicing is performed with metal layer
5
formed, metal of metal layer
5
disadvantageously adheres to the dicing saw to cause clogging or rapid wearing of the saw.
To solve this problem, a wet etching method has conventionally been employed as a method of dividing a semiconductor wafer with a thickness of 50 &mgr;m or less. Now, the method of dividing the semiconductor wafer using the wet etching method will be described.
FIGS. 37
to
39
are schematic plan views and a diagram sequentially showing the steps of the method of dividing the semiconductor wafer using the wet etching method. In addition,
FIGS. 40 and 41
are schematic cross sectional views taken along the lines J—J in
FIGS. 37 and 38
.
FIG. 42
is a schematic diagram showing the state of the semiconductor chips corresponding to the step shown in conjunction with FIG.
39
.
Referring firstly to
FIGS. 37 and 40
, a plurality of functional devices
3
are arranged and formed on the surface of a semiconductor layer
1
of a semiconductor wafer
4
d
such that they are separated from one another by a separation line region
2
. The surface of semiconductor wafer
4
d
with functional devices
3
formed thereon is applied to a reinforcing plate
21
, for example of glass, by adhesive material
31
. Thus, polishing or the like is performed for the back surface of semiconductor layer
1
and the thickness of semiconductor wafer
4
d
is made as small as 50 &mgr;m or less. A metal layer
5
is formed on the entire surface of thin semiconductor wafer
4
d
. Metal layer
5
is patterned by means of usual photolithography and left on the back surface of semiconductor layer
1
in the position corresponding to functional device
3
. Semiconductor wafer
4
d
is wet etched using the patterned metal layer
5
as a mask.
Referring to
FIG. 41
, the wet etching forms a groove passing through semiconductor layer
1
, so that semiconductor wafer
4
d
is divided into a plurality of semiconductor chips
10
d
. In this state, semiconductor chips
10
d
and reinforcing plate
21
are dipped into organic solvent for melting adhesive material
31
.
Referring to
FIGS. 39 and 42
, the dipping in organic solvent
50
allows adhesive material
31
to melt, so that semiconductor chips
10
d
come off from reinforcing plate
21
.
FIG. 43
is a perspective view schematically showing the structure of separate semiconductor chip
10
d
obtained from the wet etching. In addition,
FIGS. 44 and 45
are schematic cross sectional views taken along the lines K—K and L—L in FIG.
43
.
Referring to
FIGS. 43
to
45
, in the separate semiconductor chip
10
d
obtained from the above mentioned wet etching, functional device
3
is formed on the surface of semiconductor layer
1
, and a region
2
b
for separation of chips, on which the device has not been formed, surrounds functional device
3
. Metal layer
5
is also formed on the entire back surface of semiconductor layer
1
, with its ends outwardly protruding from the ends of the back surface of semiconductor layer
1
. In addition, the sides of semiconductor layer
1
is made narrower as closer to the back surface with metal layer
5
from the surface with functional device
3
.
According to the method using the wet etching, clogging of a dicing saw with metal layer
5
does not occur as a dicing method is not employed.
In this method, however, semiconductor chips
10
d
would scatter in organic solvent
50
as shown in
FIGS. 39 and 42
. With semiconductor chip
10
d
thus scattered and not regularly arranged, a significant amount of time is required for picking up semiconductor chips
10
d
by handling with pincette.
Furthermore, semiconductor chips
10
d
collide with one another or with a recipient many times when recovering the scattered chips moving them to another recipient in the atmosphere after they are dried. Thus, many scratches are formed and a number of fragments adhere to the surface of semiconductor chips
10
d
, thereby deteriorating the appearance of most semiconductor chips
10
d.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problems, and an object of the present invention is to provide a semiconductor device for which clogging or wearing of a dicing saw is prevented, recovery of semiconductor chips by a pincette is facilitated, and deterioration of the appearance of semiconductor chips are not easily allowed, as well as to provide a method of manufacturing such semiconductor device.
A method of manufacturing a semiconductor device according to one aspect of the present invention includes the following steps.
A semiconductor wafer is prepared which includes a semiconductor layer having a plurality of device formation regions with mutually opposite firs
Hayashi Kazuo
Takeno Shozui
Tamaki Masahiro
Flynn Nathan
Forde Remmon R.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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