Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-06-27
2001-05-08
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S685000, C257S686000
Reexamination Certificate
active
06229217
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly relates to a semiconductor device having a structure substantially miniaturized to a chip size, i.e., a CSP (Chip Size Package) structure, and a method of manufacturing such a semiconductor device.
BACKGROUND OF THE INVENTION
Miniaturization of a semiconductor device is in progress so as to achieve a high-density semiconductor device for use on a printed circuit board. Recently, a semiconductor device substantially miniaturized to a chip size has been developed. The structure of such a miniaturized semiconductor device is called a CSP structure. Japanese Publication of Unexamined Patent Application No. 121002/1997 (Tokukaihei 9-121002) discloses a semiconductor device having the CSP structure shown in FIG.
13
(
a
). This semiconductor device includes a semiconductor chip
42
disposed with its circuit formed surface facing up, and wires
43
for electrically connecting the semiconductor chip
42
to a wiring pattern
47
. The above publication discloses another semiconductor device having the CSP structure shown in FIG.
13
(
b
). This semiconductor device includes a semiconductor chip
64
disposed with its circuit formed surface facing down, and a bump electrode
70
for electrically connecting the semiconductor chip
64
to a wiring pattern
66
.
In FIG.
13
(
a
),
41
is a wiring component,
42
is a semiconductor chip,
43
is a wire,
44
is a resin sealing member,
45
is a throughhole,
46
is a substrate,
47
is a wiring pattern,
48
is an insulating material,
49
is an external connection-use terminal,
50
is an external connection area,
51
is an electrode,
52
is a window opening section, and
53
is an inner connection area. In FIG.
13
(
b
),
61
is a throughhole,
62
is a wiring component,
63
is an electrode,
64
is a semiconductor chip,
65
is a resin sealing member,
66
is a wiring pattern,
67
is an inner connection area,
68
is an external connection area,
69
is an external connection-use terminal, and
70
is a bump electrode.
In some devices such as portable devices, a plurality of semiconductor chips are mounted in a package so as to increase the added value and capacity of memory, etc. For example, a multi-chip module is provided with a plurality of semiconductor chips arranged parallel to each other in a package. However, such an arrangement makes it impossible to produce a package smaller than the total area of the semiconductor chips to be mounted. In order to solve the problem, a stacked package including a plurality of semiconductor chips laminated in a package to achieve a high packaging density is disclosed in Japanese Publication of Unexamined Patent Application No. 90486/1993 (Tokukaihei 5-90486).
Specifically, the semiconductor devices disclosed in the above publication are each packaged in ceramic packages and arranged in the following manner. In one of the semiconductor devices, a pair of semiconductor chips are adhered to each other with their back surfaces where a circuit is not formed facing each other, and are mounted on another pair of semiconductor chips via metal bumps. In the other semiconductor device, a pair of semiconductor chips are adhered to each other with the circuit formed surface of one semiconductor chip facing the back surface of the other semiconductor chip.
The above-mentioned stacked package is a small, high-density semiconductor device. However, a semiconductor device smaller than such a stacked package has been required. For that reason, a semiconductor device having a CSP structure as well as a stacked package structure is required to be produced.
In a semiconductor device having a CSP structure where the semiconductor chips are laminated, an adhesive agent (paste) potting method and a method using a thermo-compression sheet are utilized for bonding the semiconductor chip to the substrate, and for bonding the laminated semiconductor chips to each other.
In the potting method, if the amount of the adhesive agent is excessive, a large amount of adhesive agent spreads beyond the outer edge of the semiconductor chip. For example, as shown in FIG.
14
(
a
), when bonding semiconductor chips
81
and
82
to each other with their back surfaces facing each other, an adhesive agent
87
between the semiconductor chips
81
and
82
overflows. In addition, as shown in
FIG. 15
, in the step of wire-bonding the semiconductor chip
82
disposed on the top to an electrode section of a wiring layer
84
(before a sealing resin
89
and packaging-use external terminals
90
are formed), wiring on an insulating substrate
83
must be provided far from the side surfaces of the semiconductor chips
81
and
82
so as to keep the overflown adhesive agent
87
a
from coming into contact with a jig
92
of a wire bonder. Such an arrangement causes the package size to be increased in the end. Furthermore, as shown in FIG.
14
(
b
), when bonding the back surface of the semiconductor chip
82
to the circuit formed surface of the semiconductor chip
81
, the overflown adhesive agent
87
a
may stick to an electrode pad provided on the semiconductor chip
81
.
On the other hand, if the amount of the adhesive agent is too small, a gap is produced between the semiconductor chips
81
and
82
. This gap cannot be filled with the sealing resin
89
, thereby causing problems such as separation of the semiconductor chip
82
from the semiconductor chip
81
.
The method using a thermo-compression sheet requires the steps of placing members at the right locations. Specifically, a thermo-compression sheet having the same size as the semiconductor chip
82
must be placed accurately at a specific location on the semiconductor chip
81
. In addition, the semiconductor chip
82
must be bonded to the thermo-compression sheet so as to be located exactly on the top of the thermo-compression sheet.
In FIGS.
14
(
a
) and
14
(
b
),
85
is an insulating sheet,
86
is a metal bump, and
91
is an adhesive sheet.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a further-miniaturized semiconductor device having a stacked package structure as well as a CSP structure.
In order to achieve the above object, a semiconductor device in accordance with the present invention has a stacked package structure and a chip size package structure and is characterized in including:
an insulating substrate including a wiring layer having electrode sections;
a first semiconductor chip having a first insulating adhesion layer adhered to its back surface where a circuit is not formed, the first semiconductor chip being mounted on the wiring layer through the first insulating adhesion layer; and
a second semiconductor chip having a second insulating adhesion layer adhered to its back surface where a circuit is not formed, the second semiconductor chip being mounted on a circuit-formed front surface of the first semiconductor chip through the second insulating adhesion layer;
each of the first and second semiconductor chips being wire-bonded to the electrode section with a wire, the first and second semiconductor chips and the wire being sealed with a resin.
In the above structure, the first semiconductor chip and the second semiconductor chip are each wire-bonded to the electrode section provided on the wiring layer with the wires, and the second insulating adhesion layer is used for affixing the second semiconductor chip to the first semiconductor chip. This structure eliminates the need for wire-bonding the first and second semiconductor chips to points on the wiring layer, far from the side surfaces of the first and second semiconductor chips, considering a situation in which the excessively applied adhesive agent overflows the space between the first and second semiconductor chips. Therefore, a miniaturized, high-density semiconductor device can be realized.
Furthermore, in the case of using a thermo-compression sheet, when mounting the first or second semiconductor chip at a desired locati
Fukui Yasuki
Matsune Yuji
Narai Atsuya
Sota Yoshiki
Clark Sheila V.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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