Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-23
2003-10-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S253000, C438S255000, C438S397000, C438S404000
Reexamination Certificate
active
06635561
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device having a capacitor and to a manufacturing method suitable for the semiconductor device.
2. Background Art
In recent years, in association with miniaturization of a semiconductor device, various approaches have been taken for ensuring a sufficient amount of capacitance in a cell area that has been scaled down for increasing storage capacity in a semiconductor device having a capacitor; e.g., DRAM (dynamic random access memory). For instance, there has been studied a method of using a high dielectric film, such as Ta
2
O
5
(tantalum(V) oxide), BST (an abbreviation of Ba
x
Sr
1 to x
TiO
3
), and PZT (a ferroelectric formed from a solid solution consisting of a ferroelectric PbTiO
3
and an antiferroelectric PbZrO
3
), as a dielectric film (also called a capacitive dielectric film) sandwiched between an upper electrode and a lower electrode of the capacitor.
The dielectric constant of a high dielectric film, such as Ta
2
O
5
, is about several times that of a conventional silicon oxynitride (SiON) film. Hence, so long as the high dielectric film is used as a capacitive dielectric film of a capacitor, there can be ensured sufficient capacitance required for accumulating electric charges in the capacitor even when the surface areas of electrodes of the capacitor become smaller in accordance with the area of a miniaturized cell. (C=∈S/d C: capacitance of a capacitor, ∈: dielectric constant, S: the area of the capacitor, and d: the thickness of the dielectric film)
Each of the high dielectric films is formed in an oxidizing atmosphere. When polysilicon is used as material for electrodes of a capacitor as conventionally, the surfaces of the electrodes are oxidized, resulting in formation of a silicon oxide film having a low dielectric constant and spreading of a depletion layer. For these reasons, even when a high dielectric film is consciously used as a capacitive dielectric film, a dielectric film is formed on the surface of electrodes as a result of oxidation. Accordingly, a capacitive dielectric film becomes thick correspondingly, resulting in a drop in capacitance of a capacitor.
Because of such a problem, there has been performed a study on a capacitor having an MIM (metal/insulator/metal) structure which uses, as a lower electrode, platinum (Pt) having strong acid resistance or ruthenium (Ru) whose metallic oxide (RuO
2
) has conductivity, rather than a conventional SIS (silicon/insulator/silicon) capacitor or a MIS (metal/insulator/semiconductor) capacitor.
A related-art method of manufacturing a semiconductor device having a capacitor will now be described by reference to
FIGS. 9A through 9F
and
FIGS. 10A through 10C
.
As shown in
FIGS. 9A through 10C
, a first interlayer insulating film
101
is formed on a silicon substrate
100
. After a resist pattern
102
has been formed on the first interlayer insulating film
101
, a first hole
103
is formed in the first interlayer insulating film
101
by means of dry etching (see FIG.
9
A).
After removal of the resist pattern
102
, the first hole
103
is filled with a first conductive film
104
(e.g., polycrystalline silicon, tungsten (W), or titanium nitride (TiN)) The first conductive film
104
is deposited also on the first interlayer insulating film
101
(see FIG.
9
B).
Subsequently, the first conductive film
104
is removed from the first interlayer insulating film
101
, by means of total etch-back or chemical-and-mechanical polishing (CMP). As a result, a plug
105
of first conductive film is formed within the first hole
103
(see FIG.
9
C).
A second interlayer insulating film
106
is formed on the first interlayer insulating film
101
and on the plug
105
of first conductive film. After a resist pattern
107
has been formed on the second interlayer insulating film
106
, a second hole
108
is formed in the second interlayer insulating film
106
by means of dry etching (see FIG.
9
D). Subsequently, the resist pattern
107
is removed (see, FIG.
9
E).
Barrier metal film
109
; e.g., TiN (titanium nitride), and metal (e.g., Ru or Pt) film
110
which is to become a lower electrode (i.e., a storage node) of a capacitor are deposited, in this sequence, on the second interlayer insulating film
106
and on the second hole
108
(see FIG.
9
F). Deposition of the barrier metal film
109
is intended for preventing reaction, which would otherwise be caused when the metal film
110
, which is to become a lower electrode of a capacitor, comes into contact with the plug
105
of first conductive film, or for enhancing adhesion between the second interlayer insulating film
106
and the plug
105
of first conductive film.
Subsequently, the barrier metal film
109
and the metal film
110
which acts as a lower electrode of the capacitor are removed from the upper surface of the second interlayer insulating film
106
(see FIG.
10
A), by means of total etch-back or CMP. Here, the second hole
108
maybe embedded with an organic substance, such as resist, before removal of the barrier metal film
109
and the metal film
110
, thereby protecting the metal film
110
constituting the lower electrode of the capacitor. The organic substance may be removed after processing.
In order to increase the capacitance of a capacitor, a high dielectric film
111
; e.g., Ta
2
O
5
, BST, or PZT, is deposited on the surface of second interlayer insulating film
106
and the metal film
110
constituting the lower electrode of the capacitor. Metal film (e.g., Ru, Pt, or Pt doped with iridium (Ir) for enhancing thermal stability)
112
which is to become an upper electrode of the capacitor (i.e., a cell plate) is deposited so as to fill the second hole
108
, thus forming a resist pattern
113
(see FIG.
10
B). The resist pattern
113
is removed after dry etching, thus forming a capacitor of MIM structure (see FIG.
10
C).
At this time, when the metal film
112
constituting the upper electrode of the capacitor is formed from Ru, etching proceeds by means of reaction of Ru in O
2
gas plasma (from Ru to RuO
2
(conductive) and RuO
2
to RuO
4
(volatile)). Alternatively, the metal film
112
may be etched by means of O
2
/Cl
2
(oxygen/chlorine), CO (carbon monoxide), or CO/Cl
2
gas.
When the metal film
112
constituting the upper electrode of the capacitor is formed from Pt, the metal film
112
is etched in Cl
2
/Ar (chlorine/argon) gas plasma (roughly corresponding to sputtering etching).
Even when there is formed a capacitor of MIM structure which uses a high dielectric film as a capacitive dielectric, larger variations due to process conditions arise in a high dielectric film, particularly when BST or PZT is used. In order to ensure dielectric strength, a high dielectric film must be thick. For this reason, difficulty is encountered in thinly forming a high dielectric film, thus hindering expectation of an upward leap in capacitance of a capacitor.
The invention described in Japanese Patent Application Laid-Open No. 220101/1999 is aimed at increasing the capacitance of a capacitor by means of forming lower electrodes in a columnar shape so as to increase the surface area of the capacitor. When lower electrodes are of columnar shape, the distance between lower electrodes is abruptly reduced in association with miniaturization of a semiconductor device. As a result, etch residues arise in a bottom, and hence a short circuit is apt to arise. Another problem is that columnar lower electrodes themselves become narrow and likely to fall. Thus, the invention yields a problem in terms of reliability of a semiconductor device.
SUMMARY OF THE INVENTION
The present invention has been conceived under such circumstances and is aimed at achieving an upward leap in the capacitance of a capacitor of MIM structure and further improvements in the reliability of a semiconductor device.
According to one aspect o
Kawai Kenji
Kimura Hajime
Anya Igwe U.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
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