Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-05-25
2004-03-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S048000, C257S780000, C257S775000, C257S773000, C257S690000, C257S692000, C438S018000, C438S106000, C438S612000, C438S756000
Reexamination Certificate
active
06713881
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a conductor wire bonding structure and method in semiconductor devices, and particularly to a semiconductor device with increased wire connection strength with respect to the pads, and a method of manufacturing same.
BACKGROUND OF THE INVENTION
In semiconductor devices, the wire bonding method is well known as a method of connecting a mounted semiconductor chip to the external connection terminals of the package. In the wire bonding method, the bonding pads and inner leads of a semiconductor chip and wiring upon an insulating substrate on which a semiconductor chip is mounted (these are referred to together as “lands”) are connected with fine metal wire of gold or the like. The tip of a metal wire extending from the tip of a tool called a capillary is heated to form a ball which is compression bonded to the bonding pad of the semiconductor chip, and the conductor wire is quickly extruded to form a loop whose tip is fused to the land and cut.
In the process of manufacturing this type of semiconductor device, it is necessary to inspect the characteristics of each semiconductor chip prior to its mounting, so various characteristic tests are normally performed by means of an IC tester. In the characteristic tests, a probe card provided with a large number of probes is used and the tips of the probes are simultaneously put in contact with the bonding pads of the semiconductor chip, thus achieving the interface for testing.
However, at the time of probe contact in the aforementioned characteristic tests, the bonding pads of the semiconductor chip may be damaged and the aluminum metal on the surface may delaminate in this portion, resulting in the lower layer of titanium tungsten (TiW) or the like being exposed. In the wire bonding method, at the time of this joining, it is preferable for an alloy layer to be formed between the aluminum layer of the bonding pad and the gold or the like constituting the metal wire, in order to increase the strength of bonding. However, the delamination of aluminum due to the aforementioned probe contact decreases the surface area in which said alloy layer is formed, and as a result there is a problem in that the bonding reliability of the metal wire is decreased.
This problem becomes even more grave as the semiconductor chip becomes smaller and as the bonding pad size becomes smaller as performance increases. To wit, as the size of the bonding pad and the compression bonding ball of metal wire become smaller, the fraction damaged due to the aforementioned probe contact becomes extremely large. For example, as the diameter of the compression bonding ball of the metal wire becomes roughly 45 &mgr;m, the fraction containing probe damage exceeds 30%.
Therefore, an object of the present invention is to provide a structure and method in the wire bonding method that gives adequate connection strength between the bonding pads and conductor wire.
A further object of the present invention is to achieve the previous object while also providing a semiconductor device and its method of manufacture wherein the pitch between bonding pads is made smaller to be suitable to finer pitches.
SUMMARY OF THE INVENTION
The semiconductor device according to the present invention comprises: a semiconductor chip upon which are disposed roughly upon a straight line a plurality of bonding pads containing a first region as a connection region and a second region for making contact with a testing probe, and said first and second regions are lined up in a direction perpendicular to said straight line, a member provided with a plurality of conductors containing a third region as a connection region electrically connected to each of a plurality of external connection terminals and a securing area for securing said semiconductor chip, a plurality of conductor wires that electrically connect said first regions of said plurality of bonding pads to said third regions of said plurality of conductors, and an encapsulating member that encapsulates said semiconductor chip and said plurality of conductor wires.
It is preferable that said plurality of bonding pads comprise first bonding pads provided with said first regions toward the edge of said semiconductor chip and second bonding pads provided with said second regions toward the edge of said semiconductor chip, and said first and second bonding pads are disposed alternately roughly upon a straight line.
In addition, it is preferable that said plurality of bonding pads be rectangular in shape with their with their short sides lying in a direction along the edges of said semiconductor chip. Moreover, it is preferable that said plurality of bonding pads be formed with the width of said first region being wider than the width of said second region in the direction along the edges of said semiconductor chip.
Furthermore, it is preferable that said plurality of bonding pads have notches between said first region and said second region.
In addition, it is preferable that said member be an insulating substrate upon one surface of which said semiconductor chip is secured by adhesive, said external connection terminals are roughly spherical terminals formed on the other surface of said substrate, said encapsulating member is resin that encapsulates said semiconductor chip and said plurality of conductor wires on one surface of said substrate, and the lands as said third regions are electrically connected to said roughly spherical terminals via through holes.
The method of manufacturing semiconductor devices according to the present invention comprises: a step wherein a semiconductor chip upon which is disposed roughly upon a straight line a plurality of bonding pads containing a first region as a connection region and a second region for making contact with a testing probe, and said first and second regions are lined up in a direction perpendicular to said straight line, and a member provided with a plurality of conductors containing a third region as a connection region electrically connected to each of a plurality of external connection terminals and a securing area for securing said semiconductor chip are secured, and a step wherein a plurality of conductor wires electrically connect said first regions of said plurality of bonding pads to said third regions of said plurality of conductors.
It is preferable that said plurality of bonding pads comprise first bonding pads provided with said first regions toward the edge of said semiconductor chip and second bonding pads provided with said second regions toward the edge of said semiconductor chip, and said first and second bonding pads are disposed alternately roughly upon a straight line.
In addition, it is preferable that said connection step comprises: a first step wherein said first region of said plurality of first bonding pads are connected by conductor wire to said third regions of said plurality of conductors, and a second step wherein said first region of said plurality of second bonding pads are connected by conductor wire to said third regions of said plurality of conductors.
Moreover, it is preferable that said method further comprises a step wherein, prior to said securing step, testing of said semiconductor chip is performed by putting test probes into contact with the second regions of said plurality of bonding pads.
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Umeda Yoshikatsu
Umehara Norito
Brady III W. James
Erdem Fazli
Flynn Nathan J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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