Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-11-06
2001-05-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S279000, C438S199000, C438S705000, C438S511000, C438S514000
Reexamination Certificate
active
06232208
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and to a method of manufacturing high density semiconductor devices having improved gate electrode profiles. The present invention has particular applicability in manufacturing high density CMOS semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interleaved dielectric and conductive layers formed thereon. In a conventional semiconductor device
100
illustrated in
FIG. 1
, substrate
1
is provided with field oxide
2
for isolating an active region comprising source/drain regions
3
, and a gate electrode
4
, typically of doped polysilicon, above the semiconductor substrate with gate oxide
5
therebetween. Interlayer dielectric layer
6
, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer
8
, typically aluminum or an aluminum-base alloy, and source/drain regions
3
through contacts
7
, and to transistor gate electrode
49
. Dielectric layer
9
, typically silicon dioxide, is deposited on conductive layer
8
, and another conductive layer
10
, typically aluminum or an aluminum-base alloy, is formed on dielectric layer
9
and electrically connected to conductive layer
8
through vias
11
.
With continued reference to
FIG. 1
, conductive layer
10
is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer
12
, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer
13
deposited thereon. Protective dielectric layer
13
is typically comprises a nitride layer, such as silicon nitride (Si
3
N
4
). Alternatively, protective dielectric layer
13
may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer
13
provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer
13
, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer
10
for external connection by means of bonding pad
14
and electrically conductive wires
15
or an external connection electrode (not shown).
Although only two conductive layers
8
and
10
are depicted in
FIG. 1
for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g., five conductive metal layers. Also in the interest of illustrative convenience,
FIG. 1
does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, various circuit structures/parameters become increasingly important. For example, the profile of gate electrode
49
after etching must be substantially rectangular, i.e., the side surfaces being substantially parallel to each other and substantially perpendicular to the upper surface of semiconductor substrate
1
, to ensure optimum transistor performance and reliability.
Conventional semiconductor methodology comprises depositing a layer of polycrystalline silicon material followed by etching to form gate electrodes. However, due to the large grain size of polycrystalline silicon, it is difficult to form a polysilicon gate electrode with a substantially rectangular profile by etching.
Subsequently, ion implantation is conducted to form source/drain regions of a transistor having a targeted channel length. However, since the profile of the gate electrode is often non-rectangular and non-uniform, the channel length of the transistor is difficult to control. For example, variations in the profile of the gate electrode adversely affect the targeted channel length of the transistor, thereby affecting transistor performance. Certain non-uniformities in the profile can also cause performance degradation, e.g., transistor drive current non-uniformities and asymmetry.
Therefore, a need exists for a semiconductor device and a method of manufacturing a semiconductor device having a substantially rectangular gate electrode profile.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having a gate electrode with a substantially rectangular profile.
Another advantage of the present invention is a semiconductor device with a substantially rectangular gate electrode profile.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a semiconductor device. The method includes forming a dielectric layer on an upper surface of a semiconductor substrate and forming a conductive layer on the dielectric layer. The method also includes doping the conductive layer before patterning the conductive layer. The method further includes patterning the conductive layer to form a gate electrode having an upper surface and side surfaces, with the side surfaces being substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.
Another aspect of the present invention is a semiconductor device including a semiconductor substrate comprising monocrystalline silicon. The semiconductor device also includes a dielectric layer formed on an upper surface of the semiconductor substrate. The semiconductor device further includes a gate electrode comprising doped amorphous or microcrystalline silicon with the gate electrode side surfaces substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.
Other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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Ju Dong-Hyuk
Wu David
Advanced Micro Devices , Inc.
Rocchegiani Renzo N.
Smith Matthew
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