Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...
Reexamination Certificate
2005-03-10
2010-12-14
Gurley, Lynne A (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With electric field controlling semiconductor layer having a...
C257S335000, C257S336000, C257S337000, C257S338000, C257S339000, C257S340000, C257S341000, C257S342000, C257S343000, C257S491000, C257S492000, C257SE29024
Reexamination Certificate
active
07851883
ABSTRACT:
This invention aims at providing an inexpensive semiconductor device having a parasitic diode and lowering an hfe of a parasitic PNP transistor and a manufacturing method thereof. Such semiconductor device includes a P-type silicon substrate and a gate electrode formed above the P-type silicon substrate. The P-type silicon substrate includes an N-type well layer, an N-type buried layer, a P-type body layer, an N-type source layer formed in the P-type body layer, and a drain contact layer formed in the N-type well layer. The P-type body layer and the N-type source layer are formed by self alignment that uses the gate electrode as a mask. The N-type drain contact layer is formed opposite the N-type source layer across the P-type body layer formed below the gate electrode. The N-type buried layer is formed below the P-type body layer.
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Japanese Office Action issued Dec. 22, 2009 in Japanese Patent Application No. 2004-145584.
Inoue Masaki
Ohdaira Akira
Gebremariam Samuel A
Gurley Lynne A
Panasonic Corporation
Wenderoth , Lind & Ponack, L.L.P.
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