Semiconductor device and method of making the same

Details Semiconductor device and method of making the same Semiconductor device and method of making the same

1998-11-17

2001-01-16

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S361000, C257S362000, C257S378000

Reexamination Certificate

active

06175139

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having electrostatic protection elements for protecting an internal circuit from electrostatic breakdown.
DESCRIPTION OF THE RELATED ART
A semiconductor integrated circuit which is formed on a semiconductor substrate includes a wide variety of semiconductor elements. These semiconductor elements must be protected from breakdown due to an excessively high input voltage applied instantaneously and externally, such as a pulsed high voltage generated due to static electricity (e.g., electrostatic force).
Hitherto the invention, various techniques have been used for protecting semiconductor elements of a semiconductor integrated circuit from an electrostatic breakdown phenomenon.
However, with the ever-increasing integration of semiconductor devices and reduction in the dissipation power of the operating voltage, the structure of the semiconductor elements which form the semiconductor device has been reduced in size to meet the fine and high-density requirements. Generally, the electrostatic breakdown of the fine and high-density semiconductor elements easily occurs.
A technique (hereinafter referred to as a first conventional example) disclosed in Japanese Patent Application Laid-Open No. 63-202056 and a well-known technique (hereinafter referred to as a second conventional example) will be described as conventional techniques for protecting semiconductor elements from electrostatic breakdown.
FIG.
11
(
a
) shows an input protection circuit for a semiconductor device of the first conventional example, whereas FIG.
11
(
b
) shows the cross-sectional structure of the semiconductor elements forming the semiconductor device and being protected by the input protection circuit.
As shown in FIG.
11
(
a
), an input wire
102
has a first end connected to an input terminal
101
, and also is connected to the input gate of the internal circuit of the semiconductor device.
Specifically, an input-protection N-channel metal oxide semiconductor (MOS) transistor
103
is connected to the input wire
102
as an electrostatic protection transistor between the input wire
102
and an electric potential of V
SS
(GND potential). The gate of the input-protection N-channel MOS transistor
103
is fixed to the electric potential of V
SS
.
A protection circuit as above is formed by a single, relatively large MOS transistor. However, if a high pulse voltage is applied the MOS transistor, it performs a bipolar operation because of the “snap-back” effect (described in more detail below). Thus, FIG.
11
(
a
) shows a parasitic NPN transistor
104
as if it is placed between the input wire
102
and V
SS
potential.
As shown in the cross-sectional view of FIG.
11
(
b
), the input-protection N-channel MOS transistor
103
, which is a single MOS transistor actually forming the protection circuit, is provided on a semiconductor substrate
105
where the conductive-type surface is a P-channel. A gate electrode
107
is formed so as to surround a drain N+ diffusion layer
106
connected to the input terminal
101
, and a source N+ diffusion layer
108
is formed so as to surround the gate electrode
107
.
In this case, a parasitic NPN transistor
104
is operationally (e.g., effectively) formed as shown by broken lines in FIG.
11
(
b
). In this case, the semiconductor substrate
105
becomes the base of the parasitic NPN transistor
104
, the source N
+
diffusion layer
108
becomes the emitter, and the drain N
+
diffusion layer
106
becomes the collector. The source N
+
diffusion layer
108
is connected to V
SS
, and an input terminal formed by a metal pad is formed on the drain N
+
diffusion layer
106
.
In this way, in the first conventional example a single, large MOS transistor is formed as a semiconductor element for input protection.
Hereinbelow and referring to
FIG. 12
, an input protection circuit of the second conventional example is described.
As shown in
FIG. 12
, a resistance wire
202
is connected to an input terminal
201
. Then, the resistance wire
202
is connected to the input gate of the internal circuit of a semiconductor device.
An input-protection (PN) diode
203
and an NPN transistor
204
are connected so as to be parallel to one another between the resistance wire
202
and an electric potential of V
SS
.
Although not shown in
FIG. 12
, the NPN transistor
204
is formed by long and thin N
+
diffusion layers which are adjacent to each other and formed in parallel on a semiconductor substrate where the conductive-type surface is a P-channel. This NPN transistor is a lateral bipolar transistor. One diffusion layer is the emitter, the other diffusion layer is the collector, and the surface of the semiconductor substrate where the conductive-type surface between the layers is a P-channel.
Additionally, the input-protection PN diode
203
is formed by the aforementioned other N
+
diffusion layer and semiconductor substrate. In this way, the circuit of
FIG. 12
is formed.
As described above, the semiconductor device is highly integrated and operates at high-speed. Hence, the individual semiconductor elements which form the semiconductor device are even more finely formed with high density. Thus, if the semiconductor element is small, a defect in the semiconductor device will occur frequently due to electrostatic discharge (ESD).
Additionally, reduced dissipation power of the semiconductor device is required, and reducing voltage when the device is operated is becoming important. Thus, if the voltage is reduced, then the semiconductor elements which form the internal circuit of the semiconductor device will be easily breakable even if there is a small quantity of static electricity or a small excessive input voltage, as compared with existing semiconductor elements.
Given the technical advances in industry, a technique of protecting semiconductor elements from the aforementioned electrostatic discharge is urgently required.
In the aforementioned first conventional example, a single large MOS transistor is formed around the input terminal
101
as a protective element. When an excessive input voltage is applied to the drain N
+
diffusion layer
106
through the input terminal
101
, a breakdown will occur in the PN junction between the drain N
+
diffusion layer
106
just under the gate electrode
107
and the semiconductor substrate
105
. A large plurality of positive holes which are a great number of carriers are generated by the breakdown. These positive holes pull the substrate potential up to a positive side, and the MOS transistor is operated due to the “snap-back” effect. Then, the excessive input voltage is discharged to protect the circuit.
However, in this conventional example the insulation breakdown of the gate insulation film of the MOS transistor frequently occurs. Particularly, this frequency of insulation breakdown increases as the gate insulation film and semiconductor elements are made smaller.
The reason for the insulation breakdown easily occurring is believed to be as follows. When the aforementioned excessive input voltage is discharged, a large plurality of positive holes are introduced into the gate insulation film from the semiconductor substrate where the positive holes are formed and shifted to a positive side. The positive holes collect in the gate insulation film, and therefore an excessive voltage is applied to the gate insulation film which causes the breakdown to occur more easily than it would otherwise.
Additionally, in the NPN transistor
204
of the second conventional example, a pair of N
+
diffusion layers which are selectively provided on the semiconductor substrate function as the emitter region and the collector region, respectively, and the semiconductor substrate between these regions functions as the base region. When an excessive input voltage is applied to an input terminal, the base potential rises due to the positive holes which are generat

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