Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2004-12-08
2008-09-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S407000, C438S409000, C438S455000
Reexamination Certificate
active
07422956
ABSTRACT:
A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided. A silicon-on-insulator structure comprising a first silicon substrate having a first crystal orientation with a first insulating layer formed thereon and a first silicon layer having a second crystal orientation and a crystal plane overlying the first insulating layer is bonded to a second silicon substrate. The second silicon substrate has the second crystal orientation and a crystal plane and a second insulating layer formed thereon. The second silicon substrate comprises a line of defects created by implanting hydrogen ion into the second silicon substrate. The crystal plane of the second silicon substrate is oriented substantially orthogonal to the crystal plane of the first silicon layer. The second silicon substrate is split and removed along the line of defects leaving behind the second insulating layer and a second silicon layer on the silicon-on-insulator structure. A plurality of devices with different crystal orientations can be subsequently formed on a single, planar silicon-on-insulator structure by selectively etching the silicon-on-insulator structure down to silicon layers of different crystal orientations, growing selective epitaxial silicon layers in the etched regions, and subsequently planarizing the silicon-on-insulator structure by chemical-mechanical polishing.
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Drawings obtained from http://www.ee.byu.edu/cleanroom/EW—orientation.phtml on Sep. 19, 2007.
Notification of Transmittal of the International Preliminary Report on Patentability dated Mar. 21, 2007 issued in PCT/US2005/043398.
Cheek Jon D.
Waite Andrew Michael
Advanced Micro Devices , Inc.
Fourson George
McDermott Will & Emery LLP
Parker John M
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