Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1999-07-29
2002-09-10
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C285S054000
Reexamination Certificate
active
06448629
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the formation and construction of semiconductor devices and, more particularly, to enhancing the integrity of mechanically weak dielectric substrate layers so that interfaces between such substrate layers and hard mask layer or circuitry layers can withstand subsequently applied chemical-mechanical polishing forces.
BACKGROUND OF THE INVENTION
Referring to
FIGS. 1 through 4
, which illustrate various stages in the conventional formation of semiconductor devices, a hard mask layer
10
, typically silicon based, is deposited on a dielectric substrate layer
12
, typically carbon based. Next, a photomask
14
is formed on the top surface of hard mask layer
10
as illustrated in
FIG. 1. A
pattern is formed in photomask
14
(a step not illustrated), typically by lithography. Recesses
16
are etched, using the pattern of photomask
14
, through hard mask layer
10
and into dielectric substrate layer
12
. Recesses
16
extend only partially through dielectric substrate layer
12
, as illustrated in
FIG. 2
, when intended for lines and extend completely through dielectric substrate layer
12
when intended for vias.
After photomask
14
is removed, a metallic layer
18
is applied, for example by plating, over hard mask layer
10
and to the walls and bottom surfaces of recesses
16
. The resulting structure is illustrated in FIG.
3
. Next, those portions of metallic layer
18
on top of hard mask layer
10
are removed by chemical-mechanical polishing (CMP). The resulting structure is illustrated in FIG.
4
.
The lateral forces, applied during chemical-mechanical polishing, are transferred as shear forces to the interface
20
between hard mask layer
10
and dielectric substrate layer
12
. Such shear forces tend to cause separation of hard mask layer
10
from dielectric substrate layer
12
. It should be noted that similar shearing or tearing problems can arise during chemical-mechanical polishing when the semiconductor device is formed without a hard mask layer (i.e., when the metallic circuitry layer is applied directly to the substrate). The exposure of dielectric substrate layer
12
to the chemical solution used during chemical-mechanical polishing can have adverse effects on the nature and character of dielectric substrate layer
12
.
New, organic, low dielectric constant substrate materials typically require an inorganic hard mask layer for protection from chemical-mechanical polishing damage. A large, lateral interface between the organic material substrate layer and inorganic material hard mask layer is typically weak and, as indicated above, often cannot withstand chemical-mechanical polishing forces which are applied subsequent to metalization to remove the metallic circuitry layer above the hard mask.
Mechanical integrity of the material at interface
20
between the lower surface of the hard mask layer
10
and the upper surface of the dielectric substrate layer
12
during chemical-mechanical polishing tends to be a problem when processing materials that are softer or weaker than, for example, oxide or nitride. Although many improvements have been made to the upper interface
21
between the top surface of hard mask layer
10
and the lower surface metallic layer
18
placed on top of hard mask layer
10
, mechanical integrity is still a major problem with lower interface
20
.
The deficiencies of the conventional semiconductor devices show that a need still exists for an improved device and method of manufacture. An object of the present invention is to provide a semiconductor device and a method of manufacture able to withstand chemical-mechanical polishing forces applied during manufacture. A related object is to enhance the mechanical integrity of the dielectric substrate component of a semiconductor device.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a method for forming semiconductor devices. In accordance with the present invention, the method includes the steps of providing a substrate and applying a photomask to the substrate. Next, a selected thickness of selected parts of the substrate is removed by etching. After the photomask is removed, a cap dielectric layer is deposited onto the substrate with portions of the cap dielectric layer extending into spaces in the substrate from which parts of the substrate have been etched.
A semiconductor device, constructed in accordance with the present invention, includes a substrate having recesses extending inwardly from a surface of the substrate and a cap dielectric layer against the substrate having portions extending into the recesses in the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Mih Rebecca D.
Petrarca Kevin S.
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