Semiconductor device and method of locating a predetermined...

Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE23179

Reexamination Certificate

active

07547979

ABSTRACT:
Marking lines or patterns are formed among dummy patterns or on a reference plain of a semiconductor device requiring analysis to enable easy location of a point on the semiconductor device.

REFERENCES:
patent: 5854125 (1998-12-01), Harvey
patent: 6506623 (2003-01-01), Teshima et al.
patent: 6603162 (2003-08-01), Uchiyama et al.
patent: 6693357 (2004-02-01), Borst et al.
patent: 2001/0022399 (2001-09-01), Koubuchi et al.
patent: 2002/0061608 (2002-05-01), Kuroda et al.
patent: 2002/0175419 (2002-11-01), Wang et al.
patent: 2003/0044059 (2003-03-01), Chang et al.
patent: 2004/0033689 (2004-02-01), Ho et al.
patent: 2005/0161837 (2005-07-01), Matsui
patent: 0038153 (2001-05-01), None
English Abstract.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device and method of locating a predetermined... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and method of locating a predetermined..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of locating a predetermined... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4103017

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.