Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-03
2002-12-31
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S724000
Reexamination Certificate
active
06500750
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor devices and more particularly to the alignment of features on a semiconductor device substrate.
RELATED ART
Manufacturing semiconductor devices requires depositing various layers of materials over semiconductor device substrates and then patterning and etching the layers to form semiconductor device features. The successive steps of depositing, patterning, and etching eventually form is more complicated semiconductor device structures, such as transistors, capacitors, interconnects, and the like. Aligning the features formed at one level to a previous level requires using advanced photolithography equipment. Typically, the alignment requires an ability to detect optical contrasts from alignment marks formed in underlying layers. This can usually be accomplished by aligning the patterning layer to alignment marks through transparent films, such as silicon dioxide, or by using the surface topography created by underlying alignment marks.
However, semiconductor manufacturing is increasingly using chemical mechanical polishing (CMP) processes to planarize the substrate surface before depositing subsequent films. Planarizing the surface reduces the amount of topography that can be used for alignment purposes. Therefore, when non-transparent films are deposited over the surface of a planarized substrate, no means exist to adequately align either through the film to an underlying feature or using surface topography. Consequently, patterning process at these levels can be highly inaccurate and the resulting increase in the level of lithographic reworks (i.e. removing and re-patterning the resist) due to poor alignment can be costly and time-consuming.
Prior art methods that attempt to overcome this problem include over-polishing and upsizing alignment mark dimensions to create topography in the substrate surface. Unfortunately, the topography resulting from the over-polishing only produces smooth changes in the surface of the substrate, which provides poor contrast. Upsizing alignment mark dimension provides topography by preventing the alignment marks from completely filling with deposited material. However, this topography similarly has smooth surfaces that are difficult to use for alignment purposes.
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Grigg Philip G.
Shroff Mehul D.
Dang Phuc T.
Ho Hoai V.
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