Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-27
2001-02-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S643000, C438S675000, C438S664000
Reexamination Certificate
active
06194304
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a fabrication method therefor, and, in particular, to a semiconductor device having an interlayer dielectric and a fabrication therefor that enables fabrication at below the half-micron level.
In a semiconductor device such as an LSI, recent advances in miniaturization, integration, and multi-layering of electronic elements have raised vital technical problems concerning lowering the temperature at which interlayer dielectrics are formed, flattening those layers, and the techniques used for forming metal wiring.
To form such an interlayer dielectric, a silicon oxide layer is first grown at a low temperature by chemical vapor deposition on a substrate on which an electronic element or the like has been formed, then a vapor-phase reaction is induced between a silane compound, oxygen, or ozone and a gas containing an impurity such as phosphorus or boron to form a layer of a boron-phospho silicate glass (BPSG) to a thickness of several hundred mm to 1 &mgr;m. Subsequently, the layer is annealed at a high temperature in a nitrogen environment, to cause the BPSG film to liquefy in a high-temperature flow, to flatten it. After through-holes (contact holes) are formed in the thus-fabricated interlayer dielectric and a barrier layer of titanium or titanium nitride is formed thereon, a metal wiring layer is formed.
This flattening of the interlayer dielectric that uses a BPSG film makes use of the high-temperature flow characteristics of the BPSG film, and the flattening proceeds faster as the density of impurities in the BPSG film and the temperature of the annealing increase. To obtain a sufficient degree of flatness and fineness of the BPSG film, an annealing temperature of at least 850° C. is required.
However, to prevent the occurrence of punch-through between miniaturized MOS transistors, it is important to suppress any excessive broadening of the source and drain impurity layers caused by the annealing, and thus it is preferable to keep the processing temperature to not more than 850° C. When a layer of a silicide such as titanium silicide is formed on the surfaces of the source and drain impurity layers that configure a MOS transistor, high-temperature annealing will cause the region of the silicide layer to become broader than necessary, which leads to deterioration of the connectivity characteristics. For that reason, there is a demand for a technique that makes it possible to form this interlayer dielectric at a relatively low temperature.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a semiconductor device comprising an interlayer dielectric on a semiconductor substrate, which makes it possible to form a film at a lower temperature than that required for a conventional art interlayer dielectric using a BPSG film, which has an extremely good degree of flatness, and which also makes it possible to fabricate a highly reliable contact structure. The present invention also provides a method of fabricating such a semiconductor device.
The method of fabricating a semiconductor device in accordance with the present invention comprises:
a step of forming an interlayer dielectric on a semiconductor substrate including an electronic element;
a step of forming a through-hole in the interlayer dielectric;
a step of forming a barrier layer on surfaces of the interlayer dielectric and the through-hole; and
a step of forming a conductive layer on a surface of the barrier layer, and
wherein the step of forming an interlayer dielectric comprises at least the following steps (a) to (c):
(a) a step of forming a first silicon oxide layer by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method;
(b) a step of forming a porous second silicon oxide layer by reacting a compound including an impurity with silicon compounds and at least one substance selected from oxygen, and compounds including oxygen using a chemical vapor deposition method; and
(c) a step of annealing at a temperature of 300° C. to 850° C.
Step (a) of this method of fabricating a semiconductor device makes it possible to form an extremely flat layer by using a chemical vapor deposition method to cause a reaction between a silicon compound and hydrogen peroxide. In other words, the first silicon oxide layer formed by this step (a) is inherently highly fluid, and has superior self-flatt characteristics. The mechanism thereof is thought to be d the fact that, when silicon compound and hydrogen peroxide made to react by a chemical vapor deposition method, si is formed in the vapor phase, and the deposition of silanol on the wafer surface causes the formation of a having a high degree of fluidity.
When monosilane is used as the silicon compound, example, the reactions given by Equation 1 and 1′ below r in the formation of silanol:
SiH
4
+2H
2
O
2
→Si(OH)
4
+2H
2
Equation 1
SiH
4
+3H
2
O
2
→Si(OH)
4
+2H
2
O+H
2
Equation 1′
The silanol formed in accordance with Equations 1 a desorbs water by the polycondensation reaction of Equati to form silicon oxide.
Si(OH)
4
→SiO
2
+2H
2
O Equation 2
Examples of silicon compounds that could be used inorganic silane compounds such as monosilane, disi SiH
2
Cl
2
, SiF
4
, and CH
3
SiH
3
; and organic silane compounds such tripropylsilane and tetraethoxysilane.
The film formation of step (a) is preferably perfori under temperature conditions of 0° C. to 20° C. if the si compound is an inorganic silane compound, or under tempera conditions of 100° C. to 150° C. if the silicon compound i organic silane compound. If the temperature of this formation step is higher than the above maximum value, polycondensation reaction of Equation 2 proceeds too reducing the fluidity of the first silicon oxide layer making it difficult to obtain a good flatness. If temperature is lower than the above minimum value, the disassociated moisture will be adsorbed within the chamber and condensation will occur outside of the chamber, making it difficult to control the fabrication apparatus.
The first silicon oxide layer formed in step (a) is preferably formed to a sufficient thickness to cover any gaps in the surface of the silicon substrate. The minimum thickness of the first silicon oxide layer depends on the height of any unevenness in the surface of the silicon substrate comprising the electronic element, but this thickness is preferably 300 to 1000 nm. If the thickness of the first silicon oxide layer exceeds that maximum value, stresses in the layer itself will cause cracks to occur.
In step (b), a reaction is induced between a compound comprising an impurity, silicon compounds and at least one substance selected from oxygen and compounds comprising oxygen, to form the porous second silicon oxide layer on the first silicon oxide layer.
Not only does this second silicon oxide layer function as a capping layer, its porosity also allows any gaseous components that are generated from the first silicon oxide layer to escape. In addition to being porous, this second silicon oxide layer including an impurity such as phosphorus or boron, but preferably phosphorus, so that it can mitigate stresses within that layer by weakening the strength of bonds between Si and O molecules of the silicon oxide of that layer. A further important role of this second silicon oxide layer is that the impurity, such as phosphorus, within the silicon oxide layer functions as a getter of mobile ions, such as alkali ions, that have an adverse effect on the reliability of the electronic element. The density of the impurity within the second silicon oxide layer is preferably 1 to 6 wt % considering from the viewpoints of this gettering function and the mitigation of stresses in the film.
The second silicon oxide layer has a compressive stress of 100 to 600 MPa, so it has the function of preventing any increase in the tension stresses that occur in the first silicon oxide layer during the polycondensation, thus p
Asahina Michio
Matsumoto Kazuki
Moriya Naohiro
Morozumi Yukio
Suzuki Eiji
Anya Igwe U.
Oliff & Berridg,e PLC
Seiko Epson Corporation
Smith Matthew
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