Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2000-10-16

2001-10-02

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S758000

Reexamination Certificate

active

06297517

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a semiconductor fabrication control monitor and a method of fabricating the same.
In accordance with recent improvement in refinement and operation speed of LSIs, there are increasing demands for low resistance of the gate electrode, the source electrode and the drain electrode of a MOS transistor. As one technique to lower the resistance of the gate electrode, a polymetal structure of a laminated structure including a lower polysilicon film and an upper metal film has been proposed for the gate electrode (IEEE Transactions Electron Devices, ED-43, 1864 (1996), etc.).
A metal film used in a gate electrode having the polymetal structure is generally a tungsten film, and the resistance value of the polymetal gate electrode using a tungsten film is approximately {fraction (1/10)} of that of a silicide (WSi
x
) film.
In a polymetal gate electrode, it is necessary to form a barrier metal film of tungsten nitride (WN
x
) or titanium nitride (TiN) between a polysilicon film and a tungsten film in order to prevent an impurity introduced into the polysilicon film from diffusing into the tungsten film. Also, in a polymetal gate electrode, although the resistance value of the metal film can be lowered, there is interface resistance between the metal film and the polysilicon film.
In general, the interface resistance value Rc between the barrier metal film and the polysilicon film after barrier metal deposition is approximately 5×10
−6
&OHgr;·cm
2
in using a tungsten nitride film as the barrier metal film and is approximately 1×10
−5
&OHgr;·cm
2
in using a titanium nitride film as the barrier metal film. When the polymetal gate electrode is subjected to a heat treatment over 750° C. such as a heat treatment for source/drain activation, the interface resistance is increased again.
Accordingly, although the polymetal gate electrode is advantageous in largely lowering the resistance value in use as line resistance, when the interface resistance value is large, the advantage of low line resistance cannot be made use of but the operation speed of the transistor is disadvantageously lowered. In other words, when a MOS transistor is operated with AC (alternate current), distribution capacity generated in a gate insulating film is repeatedly charged and discharged, and hence a current flows through distribution interface resistance, which lowers the operation speed of the MOS transistor. Furthermore, there arises another problem in actual process that the interface resistance is largely increased due to the effect of a heat treatment carried out subsequently.
Accordingly, it is very significant to lower the interface resistance value in a polymetal gate electrode, and in addition, it is very significant from the viewpoint of management of the device fabrication process to measure and control the interface resistance value with a monitor.
Therefore, a semiconductor fabrication control monitor capable of measuring the interface resistance value is constructed in TEG or PCM provided on a scribe line of a semiconductor chip or semiconductor wafer, so as to monitor the interface resistance value. The term “a semiconductor device” is herein used as a concept including TEG, PCM and an actual device.
In conventional process management for the interface resistance value of a polymetal gate electrode, a monitor similar to that used for measuring the contact resistance of a contact hole or a via hole is used.
FIGS.
12
(
a
),
12
(
b
) and
12
(
c
) show a conventional semiconductor fabrication control monitor, wherein FIG.
12
(
a
) shows the plane structure, FIG.
12
(
b
) shows the sectional structure taken on line XIIb—XIIb of FIG.
12
(
a
) and FIG.
12
(
c
) shows an equivalent circuit.
The semiconductor fabrication control monitor shown in FIGS.
12
(
a
) through
12
(
c
) is generally designated as a Kelvin pattern. An insulating film
12
of a silicon oxide film is formed on a semiconductor substrate
11
, a polysilicon film
13
is formed on the insulating film
12
, a tungsten film
15
is formed on the polysilicon film
13
with an interlayer insulating film
14
sandwiched therebetween, and the polysilicon film
13
and the tungsten film
15
are electrically connected to each other through a contact
16
and a contact
18
. As described above, although a barrier metal film of tungsten nitride or titanium nitride is provided between the polysilicon film
13
and the tungsten film
15
, a laminated structure including the tungsten film and the barrier metal film is herein designated as the tungsten film
15
for convenience.
In the Kelvin pattern, for example, a constant current I is allowed to flow between a first terminal
1
and a third terminal
3
and a voltage V generated between a second terminal
2
and a fourth terminal
4
is measured, so that the interface resistance value RC in the contact
18
between the polysilicon film
13
and the tungsten film
15
can be calculated by using a relational expression, Rc=V/I.
Now, a method of fabricating the conventional semiconductor fabrication control monitor will be described with reference to FIGS.
13
(
a
) through
13
(
c
),
14
(
a
) through
14
(
e
) and
15
(
a
) through
15
(
d
). FIG.
13
(
a
) shows the plane structure of a first photomask A used for patterning the polysilicon film
13
, FIG.
13
(
b
) shows the plane structure of a second photomask B used for forming the contacts
16
and
18
in the interlayer insulating film
14
, and FIG.
13
(
c
) shows the plane structure of a third photomask C used for patterning the tungsten film
15
.
First, as is shown in FIG.
14
(
a
), after the insulating film
12
of a silicon oxide film is formed on the semiconductor substrate
11
, the polysilicon film
13
is deposited on the insulating film
12
.
Next, after applying a first resist film on the polysilicon film
13
, the first resist film is patterned by using the first photomask A of FIG.
13
(
a
), thereby forming a first resist pattern
17
A as is shown in FIG.
14
(
b
). Thereafter, the polysilicon film
13
is subjected to first etching by using the first resist pattern
17
A as a mask, thereby patterning the polysilicon film
13
as is shown in FIG.
14
(
c
).
Then, as is shown in FIG.
14
(
d
), the interlayer insulating film
14
is deposited on the entire top surface of the patterned polysilicon film
13
, and the interlayer insulating film is planarized.
Next, after applying a second resist film on the planarized interlayer insulating film
14
, the second resist film is patterned by using the second photomask B of FIG.
13
(
b
), thereby forming a second resist pattern
17
B as is shown in FIG.
14
(
e
). Thereafter, the interlayer insulating film
14
is subjected to second etching by using the second resist pattern
17
B as a mask, thereby forming the contact holes
16
and
18
in the interlayer insulating film
14
as is shown in FIG.
15
(
a
).
Then, as is shown in FIG.
15
(
b
), the tungsten film
15
is deposited on the entire top surface of the interlayer insulating film
14
.
Subsequently, after applying a third resist film on the tungsten film
15
, the third resist film is patterned by using the third photomask C of FIG.
13
(
c
), thereby forming a third resist pattern
19
as is shown in FIG.
15
(
c
). Thereafter, the tungsten film
15
is subjected to third etching by using the third resist pattern
19
as a mask, thereby patterning the tungsten film
15
as is shown in FIG.
15
(
d
). Thus, the conventional semiconductor fabrication control monitor as is shown in FIGS.
12
(
a
) and
12
(
b
) is completed.
The method of fabricating the conventional semiconductor fabrication control monitor, however, has problems that a process largely different from a process for forming a polymetal gate electrode of a transistor is necessary and that three photomasks, namely, the first, second and third photomasks A, B and C, are necessary.
Furthermore, there arises another problem that three e

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