Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2009-02-18
2010-10-19
Everhart, Caridad M (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257S406000, C257S407000, C257SE21637, C257SE21639, C257SE27064, C257SE21067
Reexamination Certificate
active
07816243
ABSTRACT:
A semiconductor device and a method of fabricating the same are described. A substrate having a PMOS area and an NMOS area is provided. A high-k layer is formed on the substrate. A first cap layer is formed on the high-k layer in the PMOS area, and a second cap layer is formed on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer. A metal layer and a polysilicon layer are sequentially formed on the first and second cap layers. The polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer are patterned to form first and second gate structures respectively in the PMOS and NMOS areas. First source/drain regions are formed in the substrate beside the first gate structure. Second source/drain regions are formed in the substrate beside the second gate structure.
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Chuang Chun-Fei
Hsu Che-Hua
Hsu Shao-Hua
Lin Cheng-I
Lin Chien-Ting
Everhart Caridad M
J.C. Patents
United Microelectronics Corp.
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