Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-22
2007-05-22
Lee, Calvin (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S300000
Reexamination Certificate
active
10998651
ABSTRACT:
A SiP (System-in-Package) having large-capacity passive elements incorporated therein or mounted thereon is provided. On an interposer made of a silicon substrate, metal substrate or glass substrate having via-holes formed therein, IC chips, or a plurality of chips, passive elements formed on a silicon substrate, metal substrate or glass substrate, are mounted in a face-up manner and re-wired en bloc on the chip. Because all of the silicon substrate, metal substrate and glass substrate are durable against high-temperature annealing for crystallizing a high-dielectric-constant material, large-capacity passive elements can be formed on the substrate which serves as an interposer or on the re-wiring of the chips to be mounted. It is also allowable that large-capacity passive elements formed on the silicon substrate, metal substrate or glass substrate is divided into chips, and that the resultant chips are mounted together with the IC chips.
REFERENCES:
patent: 6274937 (2001-08-01), Ahn et al.
patent: 6418029 (2002-07-01), McKee et al.
patent: 6617681 (2003-09-01), Bohr
patent: 2003/0199123 (2003-10-01), Siniaguine
Kananen Ronald P.
Lee Calvin
Rader & Fishman & Grauer, PLLC
Sony Corporation
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